On Tue, Jul 16, 2013 at 1:36 AM, Luís Vitório Cargnini <[email protected]> wrote: > Thank you for the answer. Indeed, I was referring to the or1k/or1200, I > didn't know that currently there are more than one implementation. I'll try > the mor1kx and see how it goes. > > One last detail, if I change the OPTION_ICACHE_WAYS to 4 it will work or > there is more to do than just that to obtain a 4-way cache ? >
Currently only up to 2-way caches are supported (although, supporting four 4-way has been on my list for a while). Implementing support for > 2-ways should be rather trivial, most of the code in the caches will work with an OPTION_xCACHE_WAYS > 2. The biggest obstacle is the replacement decision algorithm, currently a LRU (Least Recently Used) scheme is used. LRU is very simple to implement for a 2-way cache, since you can use 1 bit to implement it. For > 2-way caches, things get a bit more complicated, so to implement 4-way caches, you either have to bite the bullet and implement LRU for it or use some simpler replacement algorithm (like round-robin, "randomly" replace lines or some "pseudo-lru" where you only keep track of the most recently used and replace any of the others). Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
