On 07/16/2013 04:56 AM, Stefan Kristiansson wrote:
The LRU for 4 way is actually also not very complicated using the following trick:On Tue, Jul 16, 2013 at 1:36 AM, Luís Vitório Cargnini <[email protected]> wrote:Thank you for the answer. Indeed, I was referring to the or1k/or1200, I didn't know that currently there are more than one implementation. I'll try the mor1kx and see how it goes.One last detail, if I change the OPTION_ICACHE_WAYS to 4 it will work or there is more to do than just that to obtain a 4-way cache ?For > 2-way caches, things get a bit more complicated, so to implement 4-way caches, you either have to bite the bullet and implement LRU for it or use some simpler replacement algorithm (like round-robin,
You need a six bit vector, with bits of the form (x>y) meaning way x is older than way y
For four way this gives you (0>1), (0>2), (0>3), (1>2), (1>3), (2>3) The rest is relatively simple logic: assign way_lru[0] = !lru[0] & !lru[1] & !lru[2] assign way_lru[1] = lru[0] & !lru[3] & !lru[4] assign way_lru[2] = lru[1] & lru[3] & !lru[5] assign way_lru[3] = lru[2] & lru[4] & lru[5]Credits for this go to my former student Robert Specht, but I think this is based on some common methods.
As said in the other mail, we varied the mor1kx cache to implement this. I will put it online asap. We have a lot of stuff to integrate in our OpenRISC-based Multicore-System (http://www.optimsoc.org), but I hope I can at least put it to github within the next week.
Bye, Stefan
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