Hey Gang!
I was thinking a bit today about the OpenRISC memory copy operations and
a couple of questions popped up:
i) The OR1200 was write-through cache only, if I recall correctly; is
this the case still today? Does it at least provide write-combining?
What about mor1kx... does write-back cache work there?
ii) Does prefetch work on the or1k implementations? Does a l.ld*
stall the processor completely or can the pipeline continue to empty
until it hits an instruction dependent on the load where it only stalls
if the load isn't ready yet?
iii) It would be nice to have an instruction to clear a cache line. As
things stand now, overwriting an entire cache line still requires
reading the cache line from memory. If we could issue an instruction to
clear the line, the line would not need to be read from memory; we could
then go ahead and overwrite the entire line with new values and save
ourselves a cache line fill. Not sure if this is easily doable given
that it's a spec change (though it's an addition).
Mostly thinking out loud here...
/Jonas
_______________________________________________
OpenRISC mailing list
[email protected]
http://lists.openrisc.net/listinfo/openrisc
