On Sun, Nov 17, 2013 at 11:01 AM, Jonas Bonn <[email protected]> wrote:
> On 11/16/13 12:16, Stefan Kristiansson wrote: > >> On Sat, Nov 16, 2013 at 10:28:03AM +0100, Geert Uytterhoeven wrote: >> >>> On Sat, Nov 16, 2013 at 9:01 AM, Stefan Kristiansson >>> <[email protected]> wrote: >>> >>>> iii) It would be nice to have an instruction to clear a cache line. As >>>>> things stand now, overwriting an entire cache line still requires >>>>> reading >>>>> the cache line from memory. If we could issue an instruction to clear >>>>> the >>>>> line, the line would not need to be read from memory; we could then go >>>>> ahead >>>>> and overwrite the entire line with new values and save ourselves a >>>>> cache >>>>> line fill. Not sure if this is easily doable given that it's a spec >>>>> change >>>>> (though it's an addition). >>>>> >>>>> I can't figure out the use case for that, but I'm sure you have one. >>>> Enlighten us ;) >>>> From your description it sounds like you want to have content in the >>>> cache >>>> that is decoupled from the memory content, but still valid. >>>> That sounds scary to me. >>>> >>> This is useful for clearing pages, i.e. memset(page, 0, PAGE_SIZE). >>> If overwriting an entire cache line requires reading the cache line from >>> memory >>> first, you double the memory bus traffic, compared to you writing out the >>> new data. >>> >>> Ok, so it's specific to write-back only, I see the point now. >> So, what you want is a flush-and-clear command, that flushes the current >> data in the line, clear all data in the cache memory, set the match >> address >> to what was specified in the flush command and marks the line dirty. >> > > Almost... it doesn't need to flush the current data. It just needs to > overwrite the current cache line with zeroes and mark the line dirty. If I > subsequently fill the line with new data, some write-combining logic could > nicely make sure that the zeroes never even get written out on the memory > bus, only the new values. > > That will only work in two cases 1) the address You want to clear is the one the cache line is currently holding 2) the cache line doesn't contain valid data 1 is moot, since if the address is already in cache You Can just write to it without needing to read from main mem. to get to 2, You need to flush valid data out of the cacheline, so I think it makes sense to have it combined into the "flush-and-clear" command. > Consider memcpy: it wants to fill a cacheline with completely new values, > so there's no need to ever read in anything from "real" memory just so that > it can be overwritten with new values. If we know we are going to fill a > complete cacheline we can just: > > i) Clear the cacheline > ii) Write the new values > iii) Let the write-combining logic make sure that only the new values > ever hit the memory bus. > > And consider clearing a memory area (memset(ptr, 0, size)): > > i) Clear the cachline > ii) Oh, we're done...! The zeroes get written out by the writeback logic > and we never had to read in the contents of the memory that we're clearing. > > It would save a fair number of stalls to read memory just so that we can > erase/change it. > > It sometimes helps to think about cache as being "primary" memory and > "memory" being secondary, like a page swap where you swap out cachelines > that aren't currently in use. The primary memory operations of the > processor should target cache and the "swap out" should be invisible. You > just have to keep in mind that DMA uses "swap memory" instead of "primary > memory". I have no idea if that helps you, but give it some thought! :) > > /Jonas >
_______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
