On Sat, Nov 16, 2013 at 10:01:47AM +0200, Stefan Kristiansson wrote: > > ii) Does prefetch work on the or1k implementations? Does a l.ld* stall > > the processor completely or can the pipeline continue to empty until it > > hits an instruction dependent on the load where it only stalls if the load > > isn't ready yet? > > > > > No prefetch, is that even commonly done on the data bus? Or perhaps you > were referring to instruction fetch here?
I see what you are speaking about now, the software initiated cache prefetch (I/DCBPR), I had forgot about the existence of those in the specification. But, no, I don't think there is an implementation that use them. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
