On Fri, Nov 15, 2013 at 5:48 PM, Jonas Bonn <[email protected]> wrote:
> Hey Gang! > > I was thinking a bit today about the OpenRISC memory copy operations and a > couple of questions popped up: > > i) The OR1200 was write-through cache only, if I recall correctly; is > this the case still today? Does it at least provide write-combining? What > about mor1kx... does write-back cache work there? > > OR1200 actually have write-back support, but it was never widely used (and buggy?) mor1kx have write-through caches only, but in addition to the cache it has a store buffer to improve write performance. The store buffer is very simple though, and lacks support for write-combining (and re-ordering). > ii) Does prefetch work on the or1k implementations? Does a l.ld* stall > the processor completely or can the pipeline continue to empty until it > hits an instruction dependent on the load where it only stalls if the load > isn't ready yet? > > No prefetch, is that even commonly done on the data bus? Or perhaps you were referring to instruction fetch here? On mor1kx, loads will always cause a stall (on a cache miss), but as I mentioned above, stores can be performed without stalling the pipeline. But, as I also stated, it's very simple, so on a load (and that's *any* load, there's no address matching between the store buffer and the load) the store buffer is emptied first, then the load is performed. > iii) It would be nice to have an instruction to clear a cache line. As > things stand now, overwriting an entire cache line still requires reading > the cache line from memory. If we could issue an instruction to clear the > line, the line would not need to be read from memory; we could then go > ahead and overwrite the entire line with new values and save ourselves a > cache line fill. Not sure if this is easily doable given that it's a spec > change (though it's an addition). > > I can't figure out the use case for that, but I'm sure you have one. Enlighten us ;) >From your description it sounds like you want to have content in the cache that is decoupled from the memory content, but still valid. That sounds scary to me. Stefan
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