Hello all!
I'm working to port FPU from OpenRISC-1200 to mor1kx-cappuccino pipeline.
For testing proposes I ported "testfloat" program from ORPSoC v2 to or1k
newlib tool chain.
The initial and buggy :) Verilog is finished. The successfully tested
features are: "int32 to float32 conversion", "addition", "substruction",
exception handling and FPSCR reading/writing.
Knowing bugs are.
The "float32 to int32 conversion" fails with "rounding to inf+" mode while
converting 1.0f : the result is 2 (must be 1). Perhaps, the other bugs are
present, but I modified testing routine to stop testing process at the 1st
error.
The multiplier and divisor also generate erroneous results (not totally but
for some particular inputs).
And any comparison test leads to hang up of "testfloat". I tried to simulate
execution of floating point comparison on RTL with a simple program placed
into ROM. The test passed successfully (no pipeline hang up). Has anybody
got an idea how the bug could be found?
If somebody wants to participate in the activity or just review sources, the
Verilog could be found in https://github.com/bandvig/mor1kx/tree/withfpu
I haven't got source code of testfloat port for newlib placed in a public
version control system. So, if you need it, I'll send it in zip-archive
(~83KB) to e-mail you wish.
WBR
Andrey
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