Regarding hangs up on floating point comparison.
I run “testfloat” tool on HW (atlys board, BOOTROM_SPI_FLASH + U-Boot). I put
two printfs in function test_ab_float32_z_flag(...) around place where the
comparison is called:
// call software implemented comparison
trueZ = trueFunction( testCases_a_float32, testCases_b_float32 );
trueFlags = *trueFlagsPtr;
// call hardware implemented comparison
printf(" a: %08X b: %08X\r\n",testCases_a_float32,testCases_b_float32); //
#1
or1k_reset_fpcsr(); // restore FPEE, clear fpu exception flags, keep rounding
mode
(void) testFlagsFunctionPtr();
testZ = testFunction( testCases_a_float32, testCases_b_float32 ); // calls
syst_float32_eq/le/lt
testFlags = testFlagsFunctionPtr();
printf(" tZ: %d tF: %d\r\n",testZ,testFlags); // #2
Only 1st printf appears. Any kind (eq/lt/le) of comparison hangs up. So I
decided to run RTL simulation. I prepared a simplest test bench which includes
mor1kx core, wishbone interconnect from atlys project, but all peripherals
(including DDR) are replaced with dummies excluding ROM. Instead of
BOOTROM_SPI_FLASH I placed my simplest comparison test. The test’s source code
is:
l.movhi r0, 0
l.movhi r3, hi(0x3d820800)
l.ori r3, r3, lo(0x3d820800)
l.movhi r4, hi(0x5e93fffe)
l.ori r4, r4, lo(0x5e93fffe)
l.jal syst_float32_eq
endless_cycle:
l.nop 0x1
l.j endless_cycle
l.nop
syst_float32_eq:
lf.sfeq.s r3, r4
l.bnf f32eq_exit
l.addi r11, r0, 0
l.addi r11, r0, 1
f32eq_exit:
l.jr r9
l.nop
It operates correctly (executes l.addi r11, r0, 0, doesn’t execute l.addi r11,
r0, 1 and goes to endless_cycle).
As I’m not very familiar with Verilog simulation tools yet, it is quite
difficult to me to run RTL simulation with real program. So I’m planning to get
somewhere (perhaps from MinSoC) a model of simple SRAM with Wishbone face and
install it into my test bench on DDR’s place. It could be good experience for
such Verilog newbie as me, but It will take some time .
Andrey
From: Stefan Kristiansson
Sent: Tuesday, August 26, 2014 7:25 AM
To: BAndViG
Cc: openrisc
Subject: Re: [OpenRISC] Porting FPU from OpenRISC-1200 to mor1kx-cappuccino
pipeline
On Mon, Aug 25, 2014 at 9:09 PM, BAndViG <[email protected]> wrote:
Hello all!
I'm working to port FPU from OpenRISC-1200 to mor1kx-cappuccino pipeline.
For testing proposes I ported "testfloat" program from ORPSoC v2 to or1k
newlib tool chain.
The initial and buggy :) Verilog is finished. The successfully tested
features are: "int32 to float32 conversion", "addition", "substruction",
exception handling and FPSCR reading/writing.
Knowing bugs are.
The "float32 to int32 conversion" fails with "rounding to inf+" mode while
converting 1.0f : the result is 2 (must be 1). Perhaps, the other bugs are
present, but I modified testing routine to stop testing process at the 1st
error.
The multiplier and divisor also generate erroneous results (not totally but
for some particular inputs).
And any comparison test leads to hang up of "testfloat". I tried to simulate
execution of floating point comparison on RTL with a simple program placed into
ROM. The test passed successfully (no pipeline hang up). Has anybody got an
idea how the bug could be found?
I didn't completely understand this, where does the test fails if you can't
reproduce in simulations, on real hw?
If so, what happens if you run the the exact same test in simulations?
If somebody wants to participate in the activity or just review sources, the
Verilog could be found in https://github.com/bandvig/mor1kx/tree/withfpu
I haven't got source code of testfloat port for newlib placed in a public
version control system. So, if you need it, I'll send it in zip-archive (~83KB)
to e-mail you wish.
Nice work so far! I'll definitely take a closer look at it.
Stefan
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