On Wed, Aug 27, 2014 at 11:16 AM, Matt Thomas <[email protected]> wrote: > > On Aug 26, 2014, at 10:27 PM, Stefan Kristiansson > <[email protected]> wrote: > >> But we digress, I agree on your main point, the SPR accesses might be >> slow. It's just an implementation detail. >> However, it's not possible (at least not in the multicore case) to use >> the main memory as a scratch area, so the motivation to have something >> else to save state to is not really about speed. > > It's nice to have the same method available for uniprocessors too. > > I'm going by my experience writing the exception handling code > for NetBSD on PowerPC. The SPRGs are required for MP support. > > BTW, the CXR SPR is described but its SPR number was never given. > Didn't find it in or1ksim either. Does it have a number? > Since it's undefined it should return 0, right? >
Yes, that looks like one of these problems Peter spoke about. Also, I don't really see the purpose of the CXR SPR, AFAICT the same info/functionality can be obtained from the CID field in the SR SPR. However, you don't need neither of them to manually access the shadow gpr files. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
