I noticed that the OpenRISC V1.1 Specification doesn't list anything analogous to the PowerPC SPRG registers. These are real useful for storing temporaries on exceptions or storing pointers to system structures (especially per-cpu ones on MP systems).
There are the ISR0-7 registers but those are defined to be readonly so they aren't very useful. Now if the fast context switching stuff is widely implemented, I probably don't need them. But that I'm not sure of (the openrisc 1200 doesn't implement them). I'd be happy that if fast context switching isn't implemented that an extra partial set (4 is enough, 8 is better) of GPR SPRs would be made available. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
