On Mon, Sep 15, 2014 at 4:56 AM, Sébastien Bourdeauducq <[email protected]> wrote: >> The Altera Quartus II v.5 reported the following number of logic >> elements: Addition unit: 684 Multiplication unit: 1530 (!!! >> parallel !!! The serial one implemented for OR1K should be smaller.) > > On a FPGA with hard multipliers, both should have approximately the same > size. However, the serial one will have those ludicrous 35 cycles of > delay... >
I think that an implementation with a hard multiplier will be smaller than a serial one. >> Division unit: 928 Square-root unit: 919 (not ported to >> OR1K) Top unit: 326 _______________________________ >> Total: 4387 > > Bloated. That's more than mor1kx itself, which already isn't quite > resource-efficient. That combined with low performance is one of the > typical plagues that frustratingly makes most Opencores projects useless... > Sure, but in my world the design cycles are: make it work, make it fast, then make it small. mor1kx is on an overall level at the 'make it small' cycle, and while there's still a lot to do in that area. As you know, we've made some good progress in that area lately (about 33% size decrease in a minimal mor1kx cappuccino setup). I think it's a mistake to have a mindset that everything that is in any of the earlier design stages should automatically be discarded as "useless" and it's then better to start off from scratch with something of your own (regardless how tempting that might be ;)). That said, there are of course cases where you come to a point where you realize that things are beyond repair (or the effort to repair becomes to large), that was one of the reasons for mor1kx (another was the license of or1200). Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
