On 09/01/2014 01:04 AM, BAndViG wrote: > Yes, I have. As I wrote previously, I run "testfloat" on SoC generated > for Atlys board (based on Xilinx Spartan-6 FPGA). In the SoC the core > operates on 50 MHz.
That's still slow, though I remembered it to be worse than that. A reasonable frequency on Spartan-6 is 83MHz. > Regarding the code. As I see you distribute your code under GPL v3. I > prefer BSD-like or LGPL-like to be able to link with proprietary > modules. So, I'm going to use your implementation for consultation only. Well, the code I've released more recently is BSD, and I wouldn't mind re-licensing that under BSD too... Sébastien _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
