On Tue, Sep 2, 2014 at 8:55 PM, BAndViG <[email protected]> wrote: > By the way, the longest post PAR path reported by ISE is not related to FPU: > > Source: > mor1kx0/mor1kx_cpu0/cappuccino.mor1kx_cpu/mor1kx_execute_ctrl_cappuccino/ctrl_alu_result_o_14 > (FF) > Destination: > mor1kx0/mor1kx_cpu0/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[0].way_data_ram/Mram_mem1 > (RAM) > Requirement: 20.000ns > Data Path Delay: 19.281ns (Levels of Logic = 10) > > The same to other long paths. > So, the clock value of 50MHz isn't limited by FPU logic.
Well, that path is probably caused by the FPU logic, which goes through ctrl_alu_result. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
