Yes, I have. As I wrote previously, I run "testfloat" on SoC generated for
Atlys board (based on Xilinx Spartan-6 FPGA). In the SoC the core operates
on 50 MHz. I'm not sure I understand you mean talking "extremely slow". Do
you mean that too many cycles per operation? As far as I understand the
multiplier and divisor implement serial algorithms.
Regarding the code. As I see you distribute your code under GPL v3. I prefer
BSD-like or LGPL-like to be able to link with proprietary modules. So, I'm
going to use your implementation for consultation only. By the way, the
another source for consultation I have is GPLed OpenSPARC T1/T2.
Generally speaking, personally I'am interested in a BSD-like (LGPL-like)
licensed core with performance of ARM Cortex-A8/A9 level (not in "yet
another super tiny controller"), with quite powerful 32/64 bits FPU, but
without fancy DSP-like/Vector instructions (I prefer to design DSP
functionality in hardware) written on Verilog. I haven't found a core that
meet all of the conditions. So, I've decided to take participation in OR1K
"upgrade". Perhaps, it means that OR1200 FPU have to be redesigned ...
almost completely.
Andrey
-----Исходное сообщение-----
From: Sébastien Bourdeauducq
Sent: Sunday, August 31, 2014 7:38 PM
To: [email protected]
Subject: Re: [OpenRISC] Porting FPU from OpenRISC-1200
tomor1kx-cappuccinopipeline
On 08/31/2014 11:37 PM, BAndViG wrote:
Status update.
f2i conversion is fixed. Now all testfloat's f2i and i2f tests passes.
The Verilog could be found in
https://github.com/bandvig/mor1kx/tree/withfpu
Have you tried synthesizing this thing? Last time I did, that FPU was
extremely slow and extremely bloated even by OR1200 standards, making it
completely unusable and good for a one-way trip to the depths of the
trashbin. I recommend doing some reality-checking before touching this
code...
Sébastien
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