On 09/28/2014 08:29 PM, jurand wrote: > Hi, > > I am trying to run linux kernel on OpenRisc in RTL simulator. I prepared > vmlinux and successfully run it in or1ksim, using objcopy i create > vmlinux.bin and memory initialization file (using bin2vmem). What i see in > simulator is that processor starts reading from reset vector address 0x100, > after reading 0x118 addr jumps to 0x298000, after this procesor is reading > data from high addresses and after reading from 0x29813C address it jumps to > 0xA00 which according to documentation is iTLB miss exception. > > Does anyone know what is wrong?
Looks like pretty reasonable behavour... i) Processor starts at reset vector and does some setup before enabling MMU. ii) Once MMU is enabled it starts reading from "high addresses" (virtual addresses) that the MMU translates to physical addresses iii) The iTLB miss exception is, of course, expected because the first access to any page results in a TLB miss ...so the question is: is that where it gets stuck? Are you using the HW accelerated page table walking? Which implementation (or1200, mor1kx,...)? /Jonas _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
