>> simple.dts <http://openrisc.2316802.n4.nabble.com/file/n4642100/simple.dts> >> - used device tree > >This is maybe where the problem is, you have defined a memory of 128MB, >do you really have that much memory in your simulation?
Yes i have. >> 2. Processor is reading from addresses 0x100-0x118, high addresses like >> 0x17E000, C00FE948, 0x42088, C01401A8, which according to Your replies is >> probably correct. > >The addresses aren't necessarily going to say us much, since they are >specific to your kernel build (except for exception vectors and such >of course) I ran simulation in open risc simulator with trace option, loged addresses and data from RTL simulation, and compared this. Tracer from OR simulator gives assembler instructions so maybe this will tell you something. About 74 thousands read operations are the same in RTL sim and OR sim. Differences starts after l.addi assembler instruction: RTL sim | OR SIMULATAOR ----------------------+----------------------------------------------------------------- @c015851c 18a0d00d | c015851c: 18a0d00d l.movhi r5,0xd00d r5 = d00d0000 flag: 0 @c0158520 84830000 | c0158520: 84830000 l.lwz r4,0x0(r3) r4 = d00dfeed flag: 0 @c0158524 a8a5feed | c0158524: a8a5feed l.ori r5,r5,0xfeed r5 = d00dfeed flag: 0 @c0158528 e4042800 | c0158528: e4042800 l.sfeq r4,r5 flag: 1 @c015852c 0c00003c | c015852c: 0c00003c l.bnf 0x3c flag: 1 *@c0158530 9c800000 | c0158530: 9c800000 l.addi r4,r0,0x0 r4 = 00000000 flag: 1 @c015861c 1860c017 | c0158534: 85630008 l.lwz r11,0x8(r3) r11 = 00000038 flag: 1* Does it tell you something? -- View this message in context: http://openrisc.2316802.n4.nabble.com/OpenRISC-booting-Linux-on-openrisc-in-RTL-simulator-iTLB-miss-tp4642095p4642105.html Sent from the OpenRISC mailing list archive at Nabble.com. _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
