On 16.01.2012 10:30, Andy Polyakov wrote: > Are you aware of any quantitative PLL characteristics that can be > relevant in the context? Can *you* argue in favor of the hypothesis? > It's essential that somebody else but me argues to confirm or dismiss it.
Unfortunately I lack the math needed to do a formal analysis. It is only my understanding of how PLLs work (a feedback loop adjusting an internal oscillator so that the output is phase locked to an input signal) why I am speculating on this. If the processor runs on one clock and depends on another clock (e.g. driving the memory) the observed effects will depend on phase difference between these clocks (e.g. what phase the slower memory controller is at when the processor requests an access). In the case of perfect clock sources the measured phase difference will have a period dependent on least common multiplier of their periods. In praxis the feedback loop will exhibit both deterministic (e.g. quantization) and random (thermal) noise. For example if the common input clock changes, feedback loops in both PLLs go through their transfer functions until they stabilize on the new frequency. The resulting jitter will probably appear quite random, but is not. Add to that other deterministic events such as DRAM refresh - this will again introduce periodes depending on the LCM of the used time intervals. Guessing what part of the observed jitter is real entropy and what is caused by a complicated but deterministic process is very hard. There are quite a few articles dealing with PLL jitter such as http://www.designers-guide.org/Analysis/PLLjitter.pdf Regards -- Stano ______________________________________________________________________ OpenSSL Project http://www.openssl.org Development Mailing List openssl-dev@openssl.org Automated List Manager majord...@openssl.org
