Re: [PEDA] Protel 99se Polygon Pour Problem

[H. Selfridge]

Look at your design rules.  Is the hole a 'no_net' and the polygon assigned 
to something like 'ground'?  Your design rules may be set such that the 
clearance between unlike nets is too big for the space and polygon line 
width.  You get funky results when you try to force a polygon into a space 
that can't satisfy the width and clearance design rules.

The design rules for the change have to match the original design rules.
At 01:41 PM 2/24/2005, you wrote:
Gentlepeople,
        I've got a problem with a polygon pour that I can't seem to solve. I
have to modify an existing PCB footprint (new mounting holes are larger)
which then errors on the polygon. I try to redraw the polygon and the darn
thing won't fill in completely. It also seems to partially draw over
existing copper (sort of runs up to an existing trace ) even though I don't
have the checkbox set. This seems to be with this ddb only and I have tried
to repair it to no avail. Copying the pcb didn't help either. Any
suggestions? Thanks.
Dan Enslen
Texas Instruments Tucson
520.746.7324
[EMAIL PROTECTED]
snip

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