Did you check to see if the via is indeed a through hole one or perhaps it's set to a buried one in which case it wouldn't connect to a top or bottom polygon but still show it's connected to gnd. Protel shows a buried via the same as a thru hole so you wouldn't necessarily notice it's different, only way to tell is double click and check the start and end layers.
Best regards, Casey. -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Nukien Sent: March 9, 2005 4:11 PM To: Protel EDA Discussion List Subject: Re: [PEDA] Weird - via won't join GND polygons Checked the netlist. It's clean - only one GND net. Just for the hey of it, I did a "Clear all nets", then re-updated the pcb from the schematics. The polygons show up as NoNet, so I changed them to GND, and let them rebuild. Then dropped a via in an empty space connecting top and bottom polys. Rebuilt them ... Still bloody isolated. AND it still shows a ratsnest line to the nearest GND pad ... grrrr. -- Dean Carpenter deano at areyes com 94TT :) ----- Original Message ----- From: "Jon Elson" <[EMAIL PROTECTED]> To: "Protel EDA Discussion List" <[email protected]> Sent: Wednesday, March 09, 2005 3:09 PM Subject: Re: [PEDA] Weird - via won't join GND polygons > > > Nukien wrote: > > >Weird. Not working here. > > > >I have polygons on top and bottom layers, both on GND net. I drop a via on > >a blank spot, and it picks up the GND net just fine. I can verify that in > >the properties for the via. > > > >I then redo the polygons, they rebuild, but the via is isolated. But it > >still has the GND net associated with it, and there's a rats-nest line > >leading to the nearest pad on the GND net. If I select the via, the whole > >GND net is highlighted as you would expect. Even weirder, DRC doesn't flag > >a Broken Net error ... > > > > > One possibility is the netlist is corrupted, and has TWO different nets > both named > "GND". Scan the netlist to see if you have this. When the netlist gets > garbled, I > usually delete the netlist, create a netlist from schematic and then > load the netlist. > When this gets messed up, the update PCB from netlist usually will just > keep > scrambling things. > > Jon > > > > ____________________________________________________________ > You are subscribed to the PEDA discussion forum > > To Post messages: > mailto:[email protected] > > Unsubscribe and Other Options: > http://techservinc.com/mailman/listinfo/peda_techservinc.com > > Browse or Search Old Archives (2001-2004): > http://www.mail-archive.com/[email protected] > > Browse or Search Current Archives (2004-Current): > http://www.mail-archive.com/[email protected] > > ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected] ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
