This patch implements revision ranges for AMD64 events and masks that
may vary for certain cpus. A mask is introduced to the entry flags in
pme_amd64_entry_t that allows the specification of a start and end
revision for an event.
Signed-off-by: Robert Richter <robert.rich...@amd.com>
---
lib/pfmlib_amd64.c | 61 +++++++++-------------------------------------
lib/pfmlib_amd64_priv.h | 55 ++++++++++++++++++++++++++++++++++++++++--
2 files changed, 64 insertions(+), 52 deletions(-)
diff --git a/lib/pfmlib_amd64.c b/lib/pfmlib_amd64.c
index d07cec3..8f305de 100644
--- a/lib/pfmlib_amd64.c
+++ b/lib/pfmlib_amd64.c
@@ -75,38 +75,6 @@
#define AMD64_SEL_BASE 0xc0010000
#define AMD64_CTR_BASE 0xc0010004
-#define AMD64_FAM10H AMD64_FAM10H_REV_B
-
-typedef enum {
- AMD64_CPU_UN,
- AMD64_K7,
- AMD64_K8_REV_B,
- AMD64_K8_REV_C,
- AMD64_K8_REV_D,
- AMD64_K8_REV_E,
- AMD64_K8_REV_F,
- AMD64_K8_REV_G,
- AMD64_FAM10H_REV_B,
- AMD64_FAM10H_REV_C,
-} amd64_rev_t;
-
-static const char *amd64_rev_strs[]= {
- "?", "B", "C", "D", "E", "F", "G", "B", "C"
-};
-
-static const char *amd64_cpu_strs[]= {
- "unknown model",
- "K7",
- "K8 RevB",
- "K8 RevC",
- "K8 RevD",
- "K8 RevE",
- "K8 RevF",
- "K8 RevG",
- "Barcelona RevB",
- "Barcelona RevC",
-};
-
#define NAME_SIZE 32
static struct {
amd64_rev_t revision;
@@ -287,29 +255,21 @@ pfm_amd64_init(void)
}
static int
-is_valid_rev(int flags)
+is_valid_rev(unsigned int flags, int revision)
{
- if (flags & PFMLIB_AMD64_K8_REV_D
- && amd64_revision < AMD64_K8_REV_D)
- return 0;
-
- if (flags & PFMLIB_AMD64_K8_REV_E
- && amd64_revision < AMD64_K8_REV_E)
- return 0;
+ if (revision < from_revision(flags))
+ return 0;
- if (flags & PFMLIB_AMD64_K8_REV_F
- && amd64_revision < AMD64_K8_REV_F)
- return 0;
+ if (revision > till_revision(flags))
+ return 0;
/* no restrictions or matches restrictions */
return 1;
}
static inline pme_amd64_entry_t
-*pfm_amd64_get_event_entry(unsigned int i)
+*pfm_amd64_get_event_entry(unsigned int index)
{
- unsigned int index = i;
-
if (index >= amd64_event_count)
return NULL;
@@ -373,7 +333,8 @@ pfm_amd64_dispatch_counters(pfmlib_input_param_t *inp,
pfmlib_amd64_input_param_
* check revision restrictions at the event level
* (check at the umask level later)
*/
- if
(!is_valid_rev(pfm_amd64_get_event_entry(e[i].event)->pme_flags)) {
+ if
(!is_valid_rev(pfm_amd64_get_event_entry(e[i].event)->pme_flags,
+ amd64_revision)) {
DPRINT("CPU does not have correct revision level\n");
return PFMLIB_ERR_BADHOST;
}
@@ -408,7 +369,8 @@ pfm_amd64_dispatch_counters(pfmlib_input_param_t *inp,
pfmlib_amd64_input_param_
/* if plm is 0, then assume not specified per-event and use
default */
plm = e[j].plm ? e[j].plm : inp->pfp_dfl_plm;
- if
(!is_valid_rev(pfm_amd64_get_event_entry(e[j].event)->pme_flags))
+ if
(!is_valid_rev(pfm_amd64_get_event_entry(e[j].event)->pme_flags,
+ amd64_revision))
return PFMLIB_ERR_BADHOST;
reg.sel_event_mask =
pfm_amd64_get_event_entry(e[j].event)->pme_code;
@@ -417,7 +379,8 @@ pfm_amd64_dispatch_counters(pfmlib_input_param_t *inp,
pfmlib_amd64_input_param_
umask = 0;
for(k=0; k < e[j].num_masks; k++) {
/* check unit mask revision restrictions */
- if
(!is_valid_rev(pfm_amd64_get_event_entry(e[j].event)->pme_umasks[e[j].unit_masks[k]].pme_uflags))
+ if
(!is_valid_rev(pfm_amd64_get_event_entry(e[j].event)->pme_umasks[e[j].unit_masks[k]].pme_uflags,
+ amd64_revision))
return PFMLIB_ERR_BADHOST;
umask |=
pfm_amd64_get_event_entry(e[j].event)->pme_umasks[e[j].unit_masks[k]].pme_ucode;
diff --git a/lib/pfmlib_amd64_priv.h b/lib/pfmlib_amd64_priv.h
index f5e49f4..51dea1d 100644
--- a/lib/pfmlib_amd64_priv.h
+++ b/lib/pfmlib_amd64_priv.h
@@ -54,12 +54,61 @@ typedef struct {
unsigned int pme_flags; /* flags */
} pme_amd64_entry_t;
+#define AMD64_FAM10H AMD64_FAM10H_REV_B
+
+typedef enum {
+ AMD64_CPU_UN,
+ AMD64_K7,
+ AMD64_K8_REV_B,
+ AMD64_K8_REV_C,
+ AMD64_K8_REV_D,
+ AMD64_K8_REV_E,
+ AMD64_K8_REV_F,
+ AMD64_K8_REV_G,
+ AMD64_FAM10H_REV_B,
+ AMD64_FAM10H_REV_C,
+} amd64_rev_t;
+
+static const char *amd64_rev_strs[]= {
+ "?", "B", "C", "D", "E", "F", "G", "B", "C"
+};
+
+static const char *amd64_cpu_strs[]= {
+ "unknown model",
+ "K7",
+ "K8 RevB",
+ "K8 RevC",
+ "K8 RevD",
+ "K8 RevE",
+ "K8 RevF",
+ "K8 RevG",
+ "Barcelona RevB",
+ "Barcelona RevC",
+};
+
/*
* pme_flags values
*/
#define PFMLIB_AMD64_UMASK_COMBO 0x1 /* unit mask can be combined */
-#define PFMLIB_AMD64_K8_REV_D 0x2 /* event requires at least rev D */
-#define PFMLIB_AMD64_K8_REV_E 0x4 /* event requires at least rev E */
-#define PFMLIB_AMD64_K8_REV_F 0x8 /* event requires at least rev F */
+#define PFMLIB_AMD64_FROM_REV(rev) ((rev)<<8)
+#define PFMLIB_AMD64_TILL_REV(rev) ((rev)<<16)
+#define PFMLIB_AMD64_K8_REV_D PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_D)
+#define PFMLIB_AMD64_K8_REV_E PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_E)
+#define PFMLIB_AMD64_K8_REV_F PFMLIB_AMD64_FROM_REV(AMD64_K8_REV_F)
+#define PFMLIB_AMD64_FAM10H_REV_C
PFMLIB_AMD64_FROM_REV(AMD64_FAM10H_REV_C)
+#define PFMLIB_AMD64_TILL_FAM10H_REV_C
PFMLIB_AMD64_TILL_REV(AMD64_FAM10H_REV_C)
+
+static inline int from_revision(unsigned int flags)
+{
+ return ((flags) >> 8) & 255;
+}
+
+static inline int till_revision(unsigned int flags)
+{
+ int till = (((flags)>>16)&255);
+ if (!till)
+ return 255;
+ return till;
+}
#endif /* __PFMLIB_AMD64_PRIV_H__ */
--
1.6.1.2
------------------------------------------------------------------------------
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