Robert,
On Thu, Feb 12, 2009 at 5:20 PM, Robert Richter <robert.rich...@amd.com> wrote:
> +
> +/* Family 10h RevD, Istanbul */
> +
> +/* 120 */{.pme_name = "READ_REQUEST_TO_L3_CACHE",
> + .pme_code = 0x4E0,
> + .pme_desc = "Read Request to L3 Cache",
> + .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_D,
> + .pme_numasks = 11,
> + .pme_umasks = {
> + { .pme_uname = "READ_BLOCK_EXCLUSIVE",
> + .pme_udesc = "Read Block Exclusive (Data cache read)",
> + .pme_ucode = 0x01,
> + },
> + { .pme_uname = "READ_BLOCK_SHARED",
> + .pme_udesc = "Read Block Shared (Instruction cache read)",
> + .pme_ucode = 0x02,
> + },
> + { .pme_uname = "READ_BLOCK_MODIFY",
> + .pme_udesc = "Read Block Modify",
> + .pme_ucode = 0x04,
> + },
> + { .pme_uname = "CORE_0_SELECT",
> + .pme_udesc = "Core 0 Select",
> + .pme_ucode = 0x00,
> + },
> + { .pme_uname = "CORE_1_SELECT",
> + .pme_udesc = "Core 1 Select",
> + .pme_ucode = 0x10,
> + },
> + { .pme_uname = "CORE_2_SELECT",
> + .pme_udesc = "Core 2 Select",
> + .pme_ucode = 0x20,
> + },
> + { .pme_uname = "CORE_3_SELECT",
> + .pme_udesc = "Core 3 Select",
> + .pme_ucode = 0x30,
> + },
Are you sure about 0x30 here? Looks strange given that CORE_2 is 0x20.
That would imply unit mask cannot be combined because they overlap.
> + { .pme_uname = "CORE_4_SELECT",
> + .pme_udesc = "Core 4 Select",
> + .pme_ucode = 0x40,
> + },
> + { .pme_uname = "CORE_5_SELECT",
> + .pme_udesc = "Core 5 Select",
> + .pme_ucode = 0x50,
> + },
same here
> + { .pme_uname = "ANY_CORE",
> + .pme_udesc = "Any core",
> + .pme_ucode = 0xF0,
^^^^
I suspect 0xF0 does not measure on all 6 cores given the unit mask codes for
individual cores.
> +/* 121 */{.pme_name = "L3_CACHE_MISSES",
> + .pme_code = 0x4E1,
> + .pme_desc = "L3 Cache Misses",
> + .pme_flags = PFMLIB_AMD64_UMASK_COMBO | PFMLIB_AMD64_FAM10H_REV_D,
> + .pme_numasks = 11,
> + .pme_umasks = {
> + { .pme_uname = "READ_BLOCK_EXCLUSIVE",
> + .pme_udesc = "Read Block Exclusive (Data cache read)",
> + .pme_ucode = 0x01,
> + },
> + { .pme_uname = "READ_BLOCK_SHARED",
> + .pme_udesc = "Read Block Shared (Instruction cache read)",
> + .pme_ucode = 0x02,
> + },
> + { .pme_uname = "READ_BLOCK_MODIFY",
> + .pme_udesc = "Read Block Modify",
> + .pme_ucode = 0x04,
> + },
> + { .pme_uname = "CORE_0_SELECT",
> + .pme_udesc = "Core 0 Select",
> + .pme_ucode = 0x00,
> + },
> + { .pme_uname = "CORE_1_SELECT",
> + .pme_udesc = "Core 1 Select",
> + .pme_ucode = 0x10,
> + },
> + { .pme_uname = "CORE_2_SELECT",
> + .pme_udesc = "Core 2 Select",
> + .pme_ucode = 0x20,
> + },
> + { .pme_uname = "CORE_3_SELECT",
> + .pme_udesc = "Core 3 Select",
> + .pme_ucode = 0x30,
> + },
Same question here.
> + { .pme_uname = "CORE_4_SELECT",
> + .pme_udesc = "Core 4 Select",
> + .pme_ucode = 0x40,
> + },
> + { .pme_uname = "CORE_5_SELECT",
> + .pme_udesc = "Core 5 Select",
> + .pme_ucode = 0x50,
> + },
Same here.
> + { .pme_uname = "ANY_CORE",
> + .pme_udesc = "Any core",
> + .pme_ucode = 0xF0,
> + },
Same
> + { .pme_uname = "ALL",
> + .pme_udesc = "All sub-events selected",
> + .pme_ucode = 0xF7,
> + },
> + },
> + },
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