Ok, thanks Stephane. I was starting to think that it couldn't be done with just hardware but wanted to make sure.
--alexshye On 5/16/07, Stephane Eranian <[EMAIL PROTECTED]> wrote:
Hello Alex, On Wed, May 16, 2007 at 02:17:54PM -0700, Alex Shye wrote: > Hi all, > > I am working on a project in which low-overhead memory reference sampling is > necessary. If possible, I would like to be able to use hardware performance > monitor support for this. I was hoping to get some feedback/thoughts on a > couple issues: > > 1) On Itanium systems, memory reference sampling is trivial with the D-EAR > functionality. However, the systems I am working on are either AMD Opterons That's not quite true even on Itanium. Remember that DEAR only capture missing loads. It does not capture loads that it in L1D nor any stores. So you cannot really capture a trace, not even a statistical trace. > or Intel Core 2s, and it is unclear if this information can be gathered. I don't think it can on Core 2 nor Opteron. > The first thought is to use precise event-based sampling to gather > architectural state and trying to recreate the effective address. However, > PEBS is limited to a few specific counters. Also, the correct architectural To few specific events, none of which would help you narrow this down to loads and stores. > state may not be enough to calculate the effective address without the > correct memory state. Any thoughts? > I fthink you are out of luck on this. > 2) Supposing HPM+PEBS is enough, does anyone have suggestions on tools? I > understand that perfmon supports PEBS but have had a harder time finding out > if Oprofile or other tools do. > I know of no other tools that supports PEBS. > 3) Any other ideas? I was considering moving to a low-overhead > instrumentation approach if this doesn't work out... > Yes, I think your best bet is to use Intel PIN instrumentation toolkit. -- -Stephane
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