Thanks for the pointer to this work, Will. The MS thesis is very interesting and close to what I am trying to accomplish.
A question about PEBS. I have seen documentation say that the precise architectural state is stored, and I think I have seen something saying that the *next* instruction pc is actually stored in the DS buffer. If anyone has worked with it already, could you help me clear this up? Thanks, --alexshye On 5/17/07, Stephane Eranian <[EMAIL PROTECTED]> wrote:
Will, On Thu, May 17, 2007 at 09:27:16AM -0400, William Cohen wrote: > > A graduate student at NCSU, Jesse Beu, has used the PEBS registers to do > this type of sampling on P4 based processors running a perfmon2 kernel. His > master's thesis describes how this was accomplished. The main problem is > the PEBS hardware doesn't directly give address information; it give > processor state information. Computing the address from the state > information is possible, but non-trivial. > > I don't think that AMD Opterons have hardware that allows that. The AMD > Family 10 processors are suppose to have some type of sampling mechanism to > allow collection of memory reference addresses. > > > Another possible suggestion is to make use of the TLB hardware and mark > pages as unreadable and then have the trap hander do some data collection. > Yes, I agree with this technique. But you probably need some kernel support to make this fast. -- -Stephane
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