Alex Shye wrote:
Hi all,
I am working on a project in which low-overhead memory reference
sampling is necessary. If possible, I would like to be able to use
hardware performance monitor support for this. I was hoping to get some
feedback/thoughts on a couple issues:
1) On Itanium systems, memory reference sampling is trivial with the
D-EAR functionality. However, the systems I am working on are either
AMD Opterons or Intel Core 2s, and it is unclear if this information can
be gathered. The first thought is to use precise event-based sampling
to gather architectural state and trying to recreate the effective
address. However, PEBS is limited to a few specific counters. Also,
the correct architectural state may not be enough to calculate the
effective address without the correct memory state. Any thoughts?
2) Supposing HPM+PEBS is enough, does anyone have suggestions on tools?
I understand that perfmon supports PEBS but have had a harder time
finding out if Oprofile or other tools do.
3) Any other ideas? I was considering moving to a low-overhead
instrumentation approach if this doesn't work out...
Thanks in advance for your help!
--alexshye
A graduate student at NCSU, Jesse Beu, has used the PEBS registers to do this
type of sampling on P4 based processors running a perfmon2 kernel. His master's
thesis describes how this was accomplished. The main problem is the PEBS
hardware doesn't directly give address information; it give processor state
information. Computing the address from the state information is possible, but
non-trivial.
I don't think that AMD Opterons have hardware that allows that. The AMD Family
10 processors are suppose to have some type of sampling mechanism to allow
collection of memory reference addresses.
OProfile does not support the PEBS (or tagging) hardware. It just does
instruction space sampling.
Another possible suggestion is to make use of the TLB hardware and mark pages as
unreadable and then have the trap hander do some data collection.
-Will
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