We have been setting up testpoints in a very similar manner, 1 per net
(multiple allowed), bottom side.  On some boards the pads and vias are all
on a 1 mil grid, on others, a 12.5 mil grid.  But to reliably capture all
eligible testpoints, I have had to set the rule to a .1 mil grid - otherwise
, vias which clearly meet the rule are still overlooked, and I have to set
too many by hand.  But I've never seen the other problem you describe, do
they still show up as violations if you run DRC?

Mike Crist
Newport Corp.
San Luis Obispo, CA

-----Original Message-----
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Monday, April 02, 2001 3:32 AM
To: [EMAIL PROTECTED]
Subject: [PEDA] Finding & Setting Test Points




Hi,

I'm currently having a lot of trouble setting test points on my current PCB.
I've set up rules to allow a single test point per net, bottom layer only
for
SMD and thru-hole pads. The test point grid is set to 1mil.

On selecting Find & Set Test Points from the Tools menu, a number of
testpoints
are set which adhere to the rules. I've noticed that on double clicking on
these
testpoints to view their properties and then closing the dialogue box using
OK,
the testpoint then appears as a Testpoint Style violation. Closing the
dialogue
box using Cancel does not cause a violation. Has anyone else experienced
this
problem?

The reason for my wanting to view the properties of the set testpoints is
that
only 30 testpoints have been found out of 227. By viewing the properties I
was
hoping to determine the difference between vias set as testpoints and those
not.
As far as I can see there is no reason for the failure to set more
testpoints.
Am I wasting my time using feature?

Cheers

Dave

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