Ian, I'm not sure if your suggestion of vertical clearance is endorsed or just some of that famous UK wit. Your example is one of the few times this would be helpful. Through hole on top of SMT. Other combinations would drive the test and inspection guys nuts (bonkers?).
I too have the clearance blues (greens) but more often when adding dual footprint patterns to cover parts availablility issues. Similar to placing a dip for prototype and an overlayed SOIC footprint for production. I recently placed two 0805 footprints so they formed a common pad high or gnd selector for a zero ohm placement. I tried every combination of positive or negative clearance rules to get rid of the clearance violation only to give up and contruct a special three pad footprint with a three pin resistor symbol. A poor way to do it because the new symbol shows up as a single ref designator and single value. I had to make a separate symbol for pull up and one for pull down placement. -----Original Message----- From: Ian Wilson [mailto:[EMAIL PROTECTED]] Sent: Wednesday, February 06, 2002 2:44 PM To: Protel EDA Forum Subject: Re: [PEDA] Setting component clearance rules On 01:52 PM 6/02/2002 -0500, Abd ul-Rahman Lomax said: >At 02:00 PM 2/6/2002 +1100, Ian Wilson wrote: >>Negative clearances on components do not work - would be nice if they >>did. Alternatively a rule that allowed component clearance violations to >>be ignored for specific components or regions would be helpful. > >Here is what we should have. There should be two placement outline layers. >Track on these layers would represent the limits of reserved board space; >a closed outline figure would be required. Crossing of this track (not >mere contact) would generate a placement violation, as would enclosure of >one component's space by that of another except if the following feature >is added: > >A further refinement would be that additional closed figures would be >allowed *within* the outline, representing free space under the part. >(crossing of such tracks would be an error.) > >The placement outline layer would be an associated layer, i.e., it flips >with the part. > >The placement outline would also be used by any autoplacement routines. > >The design rules should also allow exceptions, as Mr. Wilson suggested. >[EMAIL PROTECTED] >Abdulrahman Lomax >Easthampton, Massachusetts USA But then why stop there - the design rules should allow us to check that the component fitting under the one with some "off-pcb" space is not too high. I may be able to fit an 0805 under a ROM socket possibly even an S0 in some parts but not a fat tant. Or what about fitting small components under the curve of a large axial cap? The height available varies with distance from the centre line of the component. I seem to remember that one of the PCB packages has a design rule system that can deal with addition and subtraction etc. Using this (and with some extra design rule functions like DistanceToComponentBorder, and/or Overlap etc that give us measures off the component(s) being DRC'ed) we could get more elaborate. Cost would be a significant slow down in DRC and great scope for complex design rules not doing what we actually wanted. Ian Wilson * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[email protected] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
