You are right when it comes to Blind vias. But a microvia is not only a blind
via. Because it is "driiled" by a laser or a similar process there are nearly
complete other requirements. One can chose the hole for a micro via between 0.05
and 0.1mm (2-4mil). The anular ring for the second layer can, theortically,  be
0 (yes zero!), because it is an Optical process using the second Layer as
reference. Because of all this reasons I need to design other vias but the
tradional mechanical drilled ones. And that is what causes the problems.
        I add some comments below.

> There are better ways. I just set a Top/Mid1 layer pair in the Stack
> Manager. I was routing on the Top layer, pressed the * or + key so that Mid
> 1 became the current routing layer, and the via which was floating was a
> blind via.
> It is also possible, of course, to edit globally a set of selected vias (or
> otherwise chosen vias) to a particular layer pair.

        Yes these may be one way. But when I use microvias mostly that will be a
problem of place. When I place "standard" vias and edit them afterwards I will
find I give away place on my PCB. Opposite, when I place Microvias and edit them
I will find a lot of DRC-errors on the other layers.  

> Further, even if one could not route interactively as I found above, one
> could use the Protel command stacking facility. While routing, P-V will
> stack interactive routing and enter Place Via mode. Say one is routing on
> the Top layer. Place Via, editing the via with Tab, as it is floating,

        Yes one more way, but you I have to change the holes and the copper sizes
forward and backward for using different vias.

> >         One more problem is that you only can chack the vias visually. No 
> >design rule
> >means no DRC. And that may cause manufacturingproblems.
        *  Argh!!! I this realy my original posting?  *
        *  I see why some people hate my "poesy"      *
> Not necessarily. I'm not sure what can be checked with DRC, but certainly
> connectivity and short checking uses the layer pairs. So if you have
> connection and no shorts, what do you care if there is a pad on a layer
> besides those for which you have intended a blind or buried via?
< -- snip -- >
> Sure, it would be nice to have DRC checking on used layer pairs, but it is
> not as dangerous as one might think if there is no such checking.

        I guess you know what I wanted to say. Different via types should have
different rules possible for anular rings and hole sizes. And for me it is not
only a "nice to have" feature. But I have to say I have not found DRC mighty
enough to check this in other EDA-tools. So protel is still on the top. But...



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