Matt,
        what reason does the DRC flag these extra tracks and vias? What is
the violation?

I believe it would probably be because they are "No Net" connections. This
is also 'possibly' why they don't follow your spacing DRC rules. For
clearance rules you have to watch the net issues because if you do not have
the board - board general clearance rule and other rules are all net
related, then the 'no net' connections may not be checked for violations.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com

Visit us at Booth 2G2-09 at CommunicAsia 2002 in Singapore June 18-21.



> -----Original Message-----
> From: Embedded Matt [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, May 23, 2002 11:10 AM
> To: Protel EDA Forum
> Subject: [PEDA] Adding extra tracks and vias.
> 
> 
> I'm working on a layout with two quad flat packs.  A
> substantial number of pins on each chip have no
> connection.  Because of the difficulty of
> hand-soldering to fine pitch pins, I would like to add
> a track and a via to each unused pin for possible use
> later.
> 
> I'm have two issues:
> 
> 1. DRC flags these extra tracks and vias as
> violations.
> 2. I get no protection from the design rules that
> specify minimum clearances and such.
> 
> I think this must be a common problem.  Is there an
> easy way to fix this without changing the schematic?
> 
> Protel 99 SE sp6.
> 
> Thanks,
> Matt 

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