At 03:36 PM 12/08/02 +1000, you wrote:
>Greetings all,
>
>I have a copy of IPC-SM-782. In it are described various recommended
>footprints for resistors, capacitors, discrete semis and ICs.
>
>I also have some documentation from Philips Semiconductors describing the
>same items.
>
>The problem is that the sizes represented in each publication are vastly
>different.
>
>What dangers are there in straying from the path prescribed by the IPC? If I
>work from the Philips documents I have smaller footprints for things like
>generic 0603 and 0805 thus allowing for tighter layouts. My copy of
>IPC-SM-782 is date 1993 - is it likely that the footprint recommendations
>would have changed in later revisions of the standard?

Linden,

I have always found the postage stamp sized IPC footprints for passives 
ridiculous.  The data in the Philips databook has always served us 
well.  We have had one manufacturer say that they would like larger pads - 
but these were much larger than the IPC std and I simply ignored them 
(production was reliable, apart from all the solder balls - they have since 
gone under).

I use the Philips book as my bible for 0603, 0805, 1206, SOT-23, SOT223 etc 
and a number of others.  I use their recommendation for wave and reflow 
footprints.  I modify the component outline (silkscreen) so it is a bar at 
each end of the component (not on each side) - I do not put a full outline 
box.  This works well as my component bars just touch (actually just don't 
touch) on a 5 mil grid and I do not have to oversize the silkscreen in two 
dimensions to simply be able to fit the silkscreen outline in.


>My previous surface mount boards have not been overly tight but this is not
>the case with the latest job - I need all the space I can get.

I find that the width and accuracy of the overlay lines can be a limiting 
factor in packing in passives.  So speak to your PCB maker to find out the 
smallest overlay line width that looks OK and what sort of registration 
they can ensure.  This will reduce the space required of your components - 
make sure you still meet the pick-and-place rules though - speak to the 
assembler and push them a little, they always want it easy.

For really tight layouts we find the via sizes can also be an issue so 
think about minimizing these as much as possible. Oh, for padless vias.

By tenting the vias you can bring them quite close to component pads.  If 
they are untented then you need a larger pad/via clearance.

Throwing layers at a tight design may not always be helpful - at least in 
the first instance. We have done a number of very small, but low volume 
boards.  The problem here is trying to optimise cost (we can't go laser 
micro-vias etc) but still make the space constraints.  Having the extra 
layers available too early in the layout has, in the past, hidden a better 
layout that we could achieve by that most critical of things, 
placement.  (These boards could also not go 0402 component sizes for cost 
reasons. They were done a number of years ago.)


Ian Wilson


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