On 07:55 AM 12/08/2002 -0600, Westfeldt, Pat said:
>Do you have a URL for this particular Phillips databook?  Thank you.
>Patrick Westfeldt, Jr.


No I don't - the data I have comes from real databooks - you know that old 
paper stuff.  It probably exists on the various Philips www sites
but I have not looked in detail.  A search for "footprints" on the Philips 
site did throw up so stuff that may be interesting but I didn't look in detail.

The SOT-23, SOT-89, SOT-223 etc wave and reflow footprints that we use are 
very similar to those in the "Surface Mounted Semiconductors" SC10a 
databook (ours is 1994 I think).  The 0603, 0805, 1206 etc to 2210 came 
from one of the passive databooks - "Ceramic Capacitors" can't recall the 
number (Tony, what was the number I emailed to you? I am at a different 
location) (ours is 1991 edition).  Both are quite old but the footprints 
have always worked very well for us.

If anyone finds them then a post here would be nice.

My main beef with the IPC footprints is that they have to be oversized as 
they take no account of solder process.  A reflow footprint can (and 
probably should) be smaller than a wave footprint. This improves density. 
(Smaller improves self-centering and reduces tombstoning - neither of which 
are a big problem with the IPC std but the point is for reflow a better 
packing density can be had without a significant drop in reliability).  A 
wave footprint has to take into account the need to pick up solder 
(oversized in the long dimension), shadowing and thieving requirements (for 
the ICs) and acceptable pad clearance for the glue dots.  The IPC seems to 
me to be just some worst-case collection of the two requirements -certainly 
an OK starting point but if packing density is critical then they are 
certainly not optimum.  This was the point in Linden's original post.

I have read somewhere (maybe "Printed Circuits Handbook" (Clyde, 4th 
Edition), possibly in some notes from elsewhere, that the heel rather than 
the toe is the most critical part of the join (from a strength 
perspective).  Reflow footprints can theoretically have no toe and still be 
reliable at least according to the data I read some year ago.  The obvious 
problem with this is the difficulty of inspection for QA - but these days 
we have that with BGA footprints don't we.  I would not suggest that anyone 
reduces their small device pads this far on my recommendation - I have 
never gone that far.

Disclaimer - few of our boards undergo massive temperature changes, and 
most are not subject to high vibration environments.  There would no doubt 
be times when I would enlarge my footprint pads to increase reliability in 
harsh environments.

I gather the SMC-plus (is that right?) footprint libraries may have 
soldering technology specific footprints - at least someone once told me 
they did.

Ian Wilson

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