Brian,

The rise time is not as important as you might think. You said 30 MHz is 
the frequency. If that means that there is 30 nanoseconds between edges, 
you can probably ignore terminations on the data lines. There will be some 
ringing for a few reflection times (perhaps 5-10 ns) but then the level 
will be stable. The multidrops on the line will add more little reflections 
anyway, and they will actually help damp the line. If you can wait 15 ns 
(for example) after the edge before sampling the data, you're home free. 
The timing signals (clocks or strobes) should be clean, so invest in proper 
terminations on these lines.

Now if 30 MHz was a typo and you really meant 300 MHz, then start adding 
resistors!

Richard

At 06:10 PM 9/27/2002 +1200, you wrote:
>I've only really got one shot at the board (I'm in New Zealand, we don't
>have much access to cheap board houses).  I'd prefer to take into the
>account the reflections etc at design time, as opposed to at re-design time.
>
>The rise/fall time of the chips is nearing 500pS (0.5nS) at the driver and
>the propagation time (of the trace) is greater than one half the rise time,
>suggesting that I should take into account transmission line theory, which
>states the line should be correctly terminated (matched).
>I was hoping that the people on this list (PCB engineers I would imagine)
>would have significant insight into the kinds of termination that could be
>used to reduce the signal distortion (from reflections etc) in this
>bidirectional situation.  I'm opposed to using that many resistors as it
>just seems so wasteful.  If possible some advice on the parallel termination
>methods would be appreciated (ie thevenin, ac and plain single resistive),
>I'm wondering what kind of things to expect from each of them...
>(I may have to work around the increased trace spacing).
>
>A secondary question is:
>Does anyone know of a low cost board house (preferably online) that does
>very cheap 6layer boards.  My current hope is for four layers and about
>US$51 per board (for about 3boards).  However if the traces are more widely
>spaced then perhaps six layers will be needed, in which case I'd have to
>look for a cheaper manufacturer.
>
>Thanks for the reply,
>Bevan Weiss
>
>----- Original Message -----
>From: "JaMi Smith" <[EMAIL PROTECTED]>
>To: "Protel EDA Forum" <[EMAIL PROTECTED]>
>Cc: "JaMi Smith" <[EMAIL PROTECTED]>
>Sent: Friday, September 27, 2002 5:10 PM
>Subject: Re: [PEDA] OT: termination for a multidrop bidirectional bus
>
>
> > Bevan,
> >
> > My first question would be why do you believe that you need any
>termination
> > to begin with?
> >
> > Is there anything in the datasheet or the specs on the logic family that
> > ledd you to believe that termination is required?
> >
> > JaMi
> >
> >
> > ----- Original Message -----
> > From: "Bevan Weiss" <[EMAIL PROTECTED]>
> > To: "Protel EDA Forum" <[EMAIL PROTECTED]>
> > Sent: Thursday, September 26, 2002 9:52 PM
> > Subject: Re: [PEDA] OT: termination for a multidrop bidirectional bus
> >
> >
> > > Hi,
> > > sorry to ask this question to you guys, but I'm more likely to get an
> > answer
> > > from the people dealing with the technology so to speak...
> > >
> > > What kind of termination is applicable for a multidrop bidirectional bus
> > > (using LVTTL signals)??  I've thought about series termination, one for
> > each
> > > driver on the bus (however that would total 256 resistors for a 32bit
>wide
> > > bus).  Thus it's not my preferred method.  I also would prefer to avoid
> > > parallel termination (or thevenin equilavent or ac termination for that
> > > matter) just because they would take up more inter-trace spacing.
> > >
> > > I'm sure that many of you have had this kind of situation before and
>have
> > > some advice.  It's for a student design project and the deadline is
> > quickly
> > > approaching.
> > >
> > > Thanks,
> > > Bevan Weiss
> >

Cheesecote Mountain CAMAC,  24 Halley Drive; Pomona, NY 10970
voice: 845 364 0211, fax: 845 362 6947,  www.cmcamac.com

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