Ivan,

I agree completely. However I did note that clocks and strobes should be 
clean, perhaps not emphatically enough though!

One way to reduce the overshoot on an unterminated trace is to really load 
the drivers. For example, by making the trace Z as low as you can (a wide 
trace and a small spacing to the ground plane).  Until the reflection 
returns, the driver sees the Z of the trace as the load.

Richard

At 10:26 AM 9/27/2002 -0400, you wrote:
> > The rise time is not as important as you might think. You said 30 MHz is
>
>I disagree.  The problem is when you have devices that are clocked by
>strobes.  Enough ringing on that strobe can cause metastability and/or
>multiple clocking.  If the ringing is bad enough to cause a non-monotonic
>transition (voltage goes one way, then reverses and goes the other way a
>little bit, before finally going the first way again) you can get multiple
>clocking.  Even if the voltage transition is monotonic, it can still be
>slowed by ringing enough to cause metastability.  It wouldn't matter if you
>had a circuit running at 100 KHz - if the rise time is too fast, you still
>need signal termination to prevent ringing.
>
>Ringing is most troublesome when you are accessing FIFO-type devices that
>have autoincrementing address counters inside them.  Metastability and
>multiple-clocking can cause some bytes to be "skipped" as the FIFO is
>emptied (or filled).  If the -CS, -RD, and -WR strobes have ringing, your
>FIFOs may not work correctly.  Ringing on the data bus is less critical, as
>long as it settles out before the active edge of the strobe signal.  In
>extreme cases, however, ringing can cause improper device operation due to
>overshoot/undershoot causing CMOS latch-up, or inducing too much noise onto
>the power and ground through input protection diodes.
>
>It's enough to make me wish there was a special family of chips with
>controlled rise/fall times.  Some PLDs and FPGAs have programmable rise/fall
>times, but I'd love to see this capability in other types of chips (standard
>logic, etc).
>
>Best regards,
>Ivan Baggett
>Bagotronix Inc.
>website:  www.bagotronix.com
>
>
>----- Original Message -----
>From: "Richard Sumner" <[EMAIL PROTECTED]>
>To: "Protel EDA Forum" <[EMAIL PROTECTED]>
>Sent: Friday, September 27, 2002 9:28 AM
>Subject: Re: [PEDA] OT: termination for a multidrop bidirectional bus
>
>
> > Brian,
> >
> > The rise time is not as important as you might think. You said 30 MHz is
> > the frequency. If that means that there is 30 nanoseconds between edges,
> > you can probably ignore terminations on the data lines. There will be some
> > ringing for a few reflection times (perhaps 5-10 ns) but then the level
> > will be stable. The multidrops on the line will add more little
>reflections
> > anyway, and they will actually help damp the line. If you can wait 15 ns
> > (for example) after the edge before sampling the data, you're home free.
> > The timing signals (clocks or strobes) should be clean, so invest in
>proper
> > terminations on these lines.
> >
> > Now if 30 MHz was a typo and you really meant 300 MHz, then start adding
> > resistors!
> >
> > Richard
>

Cheesecote Mountain CAMAC,  24 Halley Drive; Pomona, NY 10970
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