I recall some option that can be set to "include single-pin nets" -- this might give you net-names for all those unconnected pins, then the usual 'update primitives from connected copper' (or whatever) would take care of this. I can't readily test this right now, but maybe it's enough to help...
> -----Original Message----- > From: JaMi Smith [mailto:[EMAIL PROTECTED]] > Sent: Thursday, September 26, 2002 8:21 PM > <big snip> > I have two 192 pin BGA's, one 957 pin BGA, and twelve 24 pin BGA's, on which > ALL pads go to a "via", with the exception of those that are directly > connected to on the top side of the board by a trace that goes somewhere > else. > > Since this board is somewhat of a "proto" board which is being used to prove > out the operation of some 1 GHz ADC's and a big Xilink FPGA operating at 500 > MHz, I have assumed that any of the pins might be required to be accessed at > any time, to add, change, or fix something, and as a result, I have > intentionally left all of the vias attached and in the design, even though > they are not in the schematic or netlist. This results in these items being > listed as an error in the DRC. This is a major annoyance, and I wish there > was some way of eliminating these from the DRC, but since they do not have a > net name (they are all "No Net", they are kind of hard to assign to a class > and say ignore)... * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
