Igor,

that could be a solution. Building a "library" with a number of PCB files
comtaining preroutes for thes BGA components with 1mm and less pin pitch.
Thanks.

Mit freundlichem Gruß
Kind regards

Gisbert Auge
N.A.T. GmbH
www.nateurope.com



                                                                                       
                  
                    "Igor                                                              
                  
                    Gmitrovic"           An:     "Protel EDA Forum" 
<[EMAIL PROTECTED]>     
                    <igmitrovic@h        Kopie:                                        
                  
                    pm.com.au>           Thema:  Re: [PEDA] Rules and PCB library 
definitions            
                                                                                       
                  
                    13.12.2002                                                         
                  
                    03:48                                                              
                  
                    Bitte                                                              
                  
                    antworten an                                                       
                  
                    "Protel EDA                                                        
                  
                    Forum"                                                             
                  
                                                                                       
                  
                                                                                       
                  




Gisbert,

One workaround could be to keep your fanout/prereoute topology separate
from the footprint in a .pcb file and keep your footprint clean of
additional primitives. Then, when you need the footprint you could copy and
paste the fanout/prereoute section into your design. In that way you could
also optimise the position of your fanout/prereoute by rotating and
flipping it around, under the condition that the BGA is symmetrical around
any of the axis, and most of them are. Even when they are not exactly
symmetrical, it is usually one odd pin out that is a problem. That should
not be too difficult to correct.

Sounds like more work to do, but it gives you the flexibility.

Regards,

Igor

-----Original Message-----
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Friday, 13 December 2002 2:22 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Rules and PCB library definitions



Thanks, Robert, but no, this is not the explanation. I did just as you
described before routing, in order to assign the signal names to the traces
and vias which are part of the component. I also unlocked all primitives of
that component. I do a complete DRC check which runs without errors. The
traces and vias are assigned to the correct nets. They just don't obey to
rules. E.g., I set a special rule for a special via size, and assign this
size to all the vias which are part of the BGA decal by global change. The
rule will not apply for them, but for all other vias with the same
specification, which are free primitives. Global change works on these
primitives, rules don't.

Mit freundlichem Gruß
Kind regards

Gisbert Auge
N.A.T. GmbH
www.nateurope.com




                    "Robert M.
                    Wolfe"               An:     "Protel EDA Forum"
<[EMAIL PROTECTED]>
                    <wolfe.rm@sne        Kopie:
                    t.net>               Thema:  Re: [PEDA] Antwort: Rules
and PCB library definitions

                    12.12.2002
                    15:23
                    Bitte
                    antworten an
                    "Protel EDA
                    Forum"






Gisbert,
One possibility might be?
Protel is not an intelligent enough program to
automatically know after synchronization that these traces
now in a PCB and attached to pads that now have nets
associated with should also be part of that net.

That being said you need go to Design/Netlist Manager
and click the Menu button in lower left corner to bring
up menu then use "Update Free Primitive From Component Pads"
This then makes ALL traces in the whole board that are attached to
pads the net associated with that pad. So just be aware when
doing this.

My feeling is if it was built into the footprint the system should
know to make i tpart of the net automatically.

Not sure but this may be why your taces do not adhear to rules,
I would think if you had online DRC turned on you would
also see green for all these tracks vs pads as clear/short errors.

Bob Wolfe



----- Original Message -----
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, December 12, 2002 4:18 AM
Subject: [PEDA] Antwort: Rules and PCB library definitions


>
> Hi,
>
> I posted the attached message on this forum some days ago, but got no
> reponse. Perhaps someone could try to confirm this effect. If it is not a
> mistake on my side, it is a very serious bug. I would be grateful if
> someone could check if this behaviour also shows under DXP. I just
received
> my copy of DXP, but have to start the learning curve first, which will
take
> some time. So I cannot check myself now.
> Thank you.
>
> Mit freundlichem Gruß
> Kind regards
>
> Gisbert Auge
> N.A.T. GmbH
> www.nateurope.com
>
>
>
>
>                     ga@nateurope.
>                     com                  An:     "Protel EDA Forum"
<[EMAIL PROTECTED]>
>                                          Kopie:
>                     03.12.2002           Thema:  [PEDA] Rules and PCB
library definitions
>                     10:14
>                     Bitte
>                     antworten an
>                     "Protel EDA
>                     Forum"
>
>
>
>
>
>
>
> Hello group,
>
> does anyone know how to overcome the following effect:
>
> When I define e.g. a BGA component in PCB library editor and include
> fanouts and preroutes for the pads, once I have that part placed on the
> PCB, the specified rules for clearance, power connection, etc. do not
apply
> for the preroutes and fanouts, but default to the rules setting for
> "board". Is this a bug, and is there some workaround?
>
> Mit freundlichem Gruß
> Kind regards
>
> Gisbert Auge
> N.A.T. GmbH
> www.nateurope.com
>
>
>
>
>






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