Can someone explain to me how buses & hierarchy work in Protel (99SE sp6?)  

I've got a big design that's begging to be implemented using hierarchical blocks, but 
as far as I can tell the netlister is dealing with buses in a way that really limits 
the usefulness of hierarchy.  How can I successfully do the following:

1. Create subsheet 'A' with bus output X[7..0]
2. Create subsheet 'B' with bus output Y[7..0]
3. Create subsheet 'C' with bus input Z[15..0]
4. Instantiate sheets A, B, and C into toplevel sheet 'D' as follows:
 > A's port X[7..0] connected to C's port Z[15..8] 
 > B's port Y[7..0] connected to C's port Z[7..0]

Having RTFM'ed a little I read something to the effect that drawn bus wires 
essentially are just eye candy.  This seems consistent with the fact that I seem to be 
able to draw all the bus-wires and labels I want and nothing gets connected right.  
Who thought this was a good idea???

Am I screwed?

Doing the above would be trivial in a HDL (like Verilog or VHDL) and would also be not 
too hard in some other schematic packages I've used (ViewDraw for example)...there 
must be a way to do it in P99 too right????

-----Original Message-----
From: DUTTON Phil [mailto:[EMAIL PROTECTED]] 
Sent: Thursday, February 06, 2003 6:46 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Aus PCBs


Hello Ian,

You may also like to try;

Entech Printed Circuits
[EMAIL PROTECTED]

East Coast Circuits
[EMAIL PROTECTED]

regards,

Phil

-----Original Message-----
From: Ian Capps [mailto:[EMAIL PROTECTED]]
Sent: Friday, 7 February 2003 12:35 PM
To: Protel EDA Forum
Subject: [PEDA] Aus PCBs


This is OT but I would appreciate some feedback from Australian users on any Aus 
manufactures who are able to do decent Prototypes and seem to be able to keep there 
promised turnaround times.

Feel free to respond off forum.

We seem to have lost all of these in QLD.

Ian Capps
ICE PCB Design and Drafting
[EMAIL PROTECTED]






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