At 10:16 PM 2/6/2003, Peter W. Richards wrote:
Can someone explain to me how buses & hierarchy work in Protel (99SE sp6?)
It can be a tad tricky. The key is in understanding how the netlister recognises what is connected to what. And there is a program shortcoming that requires a workaround.

[... original post sequence altered for clarity ...]
Having RTFM'ed a little I read something to the effect that drawn bus wires essentially are just eye candy. This seems consistent with the fact that I seem to be able to draw all the bus-wires and labels I want and nothing gets connected right. Who thought this was a good idea???
Yes, bus-wires are *mostly* eye candy, added to make bus usage clearer to the reader. Bus ports, however, are essential in hierarchical design, and net labels and wires are the foundation of all connectivity.

I indicated an exception to the bus = eye-candy rule, and it is crucial. To connect a bus to a port or sheet entry, you can place the hot spot for a bus label on the port/sheet entry hot spot, *or* you can draw a bus-wire and place the net label on this bus-wire. See below. The Protel manual is incorrect when it says that bus-wires have no electrical effect.

I've got a big design that's begging to be implemented using hierarchical blocks, but as far as I can tell the netlister is dealing with buses in a way that really limits the usefulness of hierarchy. How can I successfully do the following:

1. Create subsheet 'A' with bus output X[7..0]
2. Create subsheet 'B' with bus output Y[7..0]
3. Create subsheet 'C' with bus input Z[15..0]
On the subsheets A and B, place an *input* port, in the first case you would name it X[0..7], in the second, Y[0..7]. You can also use descending numbers as you requested, I didn't do that here....

For every net that you want to connect on the subsheets, you must place an individual net label in a position where it will be electrically active. Every net label has a hot spot (lower left corner with a horizontal label); if this hot spot is on a wire or on the hot spot of a pin, the net connection will be effected to the wire or pin.

You must *also* place a net label for the bus itself, in such a way that Protel knows that it is connected to the port. This can be done by placing the net label hot spot on the port hot spot, but it is usually clearer and simpler to draw a bus-wire connecting to the port and place the net label on that bus-wire. Protel will follow the bus-wire back to the port and connect the on-sheet bus to the off-sheet bus.

On the subsheet C, place an *output port* named Z[0..15].

Why are input and output reversed? Because the port symbol represents to the eye and to ERC (Schematic Error Check) what is off-sheet. So, for example, an input pin on the sheet must be connected, presumably, to an output pin somewhere else in the hierarchy. On the level above, the inputs on the lower sheet will be seen as the inputs that they actually are.... If you don't follow this convention, you may have some difficulty getting a clean ERC, and clean ERCs are a mark of good design.

4. Instantiate sheets A, B, and C into toplevel sheet 'D' as follows:
 > A's port X[7..0] connected to C's port Z[15..8]
 > B's port Y[7..0] connected to C's port Z[7..0]
On the toplevel sheet, place a sheet symbol for sheets A, B, and C. Use "Create Symbol from Sheet" on the Design Menu and agree to reverse Input/Output directions. You should now have the appropriate sheet symbols and sheet entries.

The following *should* work, but it doesn't seem to, perhaps for a reason I will give below. Draw a bus wire connecting to the C sheet entry and label it A[0..15]. Draw a bus wire connecting to the A sheet entry and label it A[8..15]. Draw a bus wire connecting to the B sheet entry and label it A[0..7]. (It could have been any name, I used "A" just to emphasize that the name of a net on the top level is not necessarily the same as the name of the net on a lower level. This is *essential* for design re-use.)

Apparently, however, Protel connects sheet entry ports to buses only by explicit match of the bus number. If I am correct about this, it is a serious deficiency, I vaguely remember it having been discussed before. Where an eight-member bus connects to another eight-member bus, for example, the connections should be made by sequential match rather than by explicit numerical identity. Has this been fixed in DXP?

To make the connectivity work as desired, without monkeying with the subsheets, I do not find simple. I could go on to define a workaround, but first, does anyone else know how to make, say X[0..3] connect to Z[4..7]?

With design re-use especially, one does not want to have to modify the subsheets! In the desired case, I'd probably modify the sixteen-bit subsheet to have two explicit 8-bit busses.

If Protel supported net renaming, the matter could be accomplished on the top level. Okay, I'll describe the workaround because Protel *does* support net renaming, it is merely that it squawks about it.

on the top sheet, label the bus wire connected to the A sheet M[0..7] in stead of A[8..15]. This will connect M0 to subsheet A bit 0, etc. Then place eight wires. You can connect these wires to bus-wires appropriately if you want to make it pretty. On one side of each wire, place A8, A9, ..., A15. on the other side of the wire, place M0, M1, ..., M7. This will explicitly connect net A8 to M0, A9 to M1, etc. Obviously, I chose "M" arbitrarily, its principle qualification being that I had not used it before. When you run ERC, you will get "multiple net identifier" errors. Place No-ERC directives on the corresponding error markers.

This did it with my test.

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