>>Apparently, however, Protel connects sheet entry ports to buses only by 
explicit match of the bus number. If I am correct about this, it is a 
serious deficiency...

>>To make the connectivity work as desired, without monkeying with the 
subsheets, I do not find simple. I could go on to define a workaround, but 
first, does anyone else know how to make, say X[0..3] connect to Z[4..7]?

Yes, this is EXACTLY the problem I'm having.  Protel99's weird ideas about how to 
connect buses (as I understand them) present a significant barrier to design 
re-use--if I want my sub-module's X[7..0] output to hook to Y[15..8] in the top-level, 
I have to go back and change the sub-module to either renumber the bus [15..8], or get 
rid of the buses entirely and design in terms of single wires (yech...stone 
age...maybe I'll put the netlist on punch cards while I'm at it)

>>If Protel supported net renaming, the matter could be accomplished on the 
top level. Okay, I'll describe the workaround because Protel *does* support 
net renaming, it is merely that it squawks about it.

I'll try this approach next time...I've already gone back and hacked up the design and 
converted all 're-named' buses to single wire ports. :(

I'm sure glad someone at Protel worked on that whizzy 3D board viewer instead of 
making buses/hierarchy actually work for nontrivial designs--NOT!

On a related Protel-sabotaging-design-reuse note, is there a way to create a 
sub-module and connect one of its inputs to power or ground, without getting ERC 
errors that claim I've shorted two nets (for example GND vs. the net name inside the 

Peter W. Richards / [EMAIL PROTECTED]
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