Hello again.

I've been tossing and turning this problem over and over and stil haven't a workable solution.
I do not want every via or component pin that is in the GND net to connect to the GND plan, only certain ones; I want to control where the current enters the plane.


Putting arcs around them works, but is not correctly handled by the DRC: on one board I ended up with too many arcs and no connection to GND..
Luckily the fab house made a comment on those arcs and I could save the otherwise useless boards by specifying what arc to remove.....


Is there a way to do this that at least generates a DRC warning?
OKok I got the warning that there were primitives on the GND plane but that didn't help much: I usually have stackup and other texts/markers on every copper layer. The warning didn't specify any of them so I wrongly assumed it was moating about my texts and such.....


Maybe someone in the forum has figured this out, or has some otherwise useful comments.
Any help is (as always) greatly appreciated.


Leo Potjewijd
hardware designer
IE Keyprocessor bv.

[EMAIL PROTECTED]
+31 20 4620700



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