Please see below,


----- Original Message -----
From: "Julian Higginson" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Wednesday, June 04, 2003 6:00 PM
Subject: Re: [PEDA] eight-layer stackup

> Jami,
> you missed a few important points.
> Generating a netlist and loading it into your PCB is not hard to do. It is
> few more mouse clicks (maybe 20 seconds more work) than just hitting
> Your time is surely not that valuable, is it??

I am sure that this may work, but I was not thinking along those lines
primarily since the last big mother of a BGA board that I did was done from
an OrCAD netlist, where I don't think those options were available to me.
Also see below.

> like I said:
> generate a netlist - it gives you the option to generate single pin nets
> you want - ie a net for every unconnected pin.
> load the netlist into the PCB.

I can"t really envision a place that I would want to have a net for every
unconnected pin in the design. This seems to be jumping thru extra hoops
just to make Protel DRC happy.

I only would want a net on the unconnected BGA pins that I would want to
connect to a via so that that connection would be accessible from the back
of the PCB.

Juggling the netlist to generate all the extra nets seems to me to be an
extra step that is not going to be understood by the next guy who happens to
have to work on the design a couple of years from now when I may not be
here. Also see below.

I could also solve the problem by turning off certain rule checking, but
that is not the answer. By doing that, I may miss a real error.

I would rather have a dogbone trace and via flagged as an error, than have
to override the ability to catch another single node net that really was an

> Now, if this is not the first iteration of the PCB (ie you haven't just
> placed all the parts on the board, its possible some preroutes will have
> nets already assigned to them) And particularly if you have just changed
> nets around on pins, as happens with FPGAs at layout time. you need to go
> the net manager in the PCB editor and unlock the primitives of the
> BGA, then select all the primitives. Do a global edit on selected tracks,
> and selected VIAS to set them all to "NO NET" Then lock them all again.
> Then, you do that "update free primitives from component pads" thing.
> Now you won't have to make up any funny rules in your PCB, and you won't
> have to sit there after a DRC working out what are valid shorted nets and
> what aren't.
> It's a pain, but the only way I know to update prerouted footprints
> properly.
> Using the "update PCB" menu item does not allow this, and so when you're
> working with pre-routed BGA footprints, it is a better idea to work with
> netlists, even if it isn't as immediately convenient.

This kind of sounds like some of the things you mention here are some of the
things we all may do anyway in our approach to BGA routing. In this respect
see my parallel resopnse in this thread to Dennis.

On the other hand, juggling things around "netlist" wise, such as your
selecting vias above and then setting them to  NO NET and then locking them,
seems like much more than I want to get into. I don't ever want to have to
manually edit any net in the netlist or in the design. To me the netlist is
sacred, and I never want to have to diddle around with it. That is my on
real "baseline" in the design that I personally feel should never be

Getting back to Michael's original question in this thread: "DRC ... is
great other than the "dogbones" I had to route to the via on all the unused
pins of the BGA. Any way to create rules for this so I do not get violations
during DRC?", I simply stated that I didn't think that there was an easy way
to do it short of putting them on the schematic. What I should have said,
and what I really meant, was that I didn't think that there was an easy way
to do it short of putting them on the schematic, without playing tricks on
Protel or having to do anything non standard.

I have a very strong aversion to having to do anything non standard in
Protel, just to get things done and acceptable to Protel DRC. As discussed
in your other post on Saturday, Protel DRC is not always right.

Yes, there have been times that I have had to explain to someone that
something really was not an error, simply because Protel thought it was an
error (the error discussed in your other thread on Saturday regarding a
trace crossing a split in an unrelated plane is a perfect example).

Yes, there is a matter of personal pride in doing a design in Protel that
has no DRC "errors".

I would rather have the DRC "error", which to anyone is obviously really not
an "error" anyway, than to have to have something in the final design that
could possibly be missed or not understood by the next guy to work on the

This is why I brought up the issue in the other post as to the acceptability
of certain DRC "errors".

> -------------
> As for my board (not that I need any more help on it, it's working great!
> Its a 4 layer baord.
> 2 signal, 1 ground 1 power.
> the power and ground planes have split planes on them.
> Stackup is:
> Signal
> Signal
> All the high speed signals go on the top layer over the unbroken ground
> plane. there is only one ground plane for the majority of the PCB, the
> grounds are around connectors where I have isolated grounds for different
> I/O connections.
> The power plane IS split under the BGA because it requires 4 power rails.
> actual power supplies, ome voltage reference for the gigabit transcievers)
> could possibly do a screen dump to illustrate this if you want but I guess
> you know what they look like anyway.

Glad to see that you got the design down to 4 layers. In your previous post
you stated that you had 3 power planes, and I understood that to mean that
you had 3 planes in your design, which would have been unbalanced, as
opposed to 2 planes with 3 different supplies distributed on them via split

Can you do something like a PDF and send it to me off line?

> What I was saying, is that for a design that requires only two routing
> layers, a 6 layer board is slight overkill, no? one split power plane is
> certianly usable if you are careful. Of course the usual caveats apply -
> Your Mileage May Vary, Not Valid In All States,  For Internal Use Only,
> Is Not A Guarantee, etc etc etc, blah blah blah.

I concur that if you careful, and if it means the difference between 4 and 6
layers that it is certainly worth trying. The real question here is that of
electrical performance, and if you do not have to sacrifice anything there,
then by all means go for the 4 layer option with the split power plane. But
once again, I would say that you should not cross that gap in the power
plane with any signals, since that will cause EMC / Signal Integrity
problems. You also need to make sure that with any split plane that you
really do have adequate power distribution with good decoupling, and not to
beat a dead horse, direct connection to the planes rather than "thermal
reliefs". If you insist on using thermals, it is imperative that you check
out your final gerbers in something besides Protel, like CAMtastic, where
you can actually really see the end product planes and check to make sure
that you haven't "swiss cheesed" yourself into an open connection somewhere,
or some other problem.

> Julian


* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
* Contact the list manager:
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
* Browse or Search previous postings:
* http://www.mail-archive.com/[EMAIL PROTECTED]
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Reply via email to