> From: JaMi Smith [mailto:[EMAIL PROTECTED]

> While there may be some way somewhere to make Protel ignore 
> those dogbones
> and vias, DRC wise, I don't think that there is a way to do 
> it easily short
> of putting them on the schematic, possibly as test points, so 
> that each of
> them actually becomes a real "net" it the netlist. You could 
> turn off some
> of your Design Rules, but that would really just be asking 
> for more trouble.
> 
yeah there is a way:

Don't use synchronisation in the ddb, use NETLIST GENERATION and NETLIST
LOADING. 

In the netlist generation in schematic, you can tell it to include unnamed
single pin nets. You will then get nets assigned to all your unused pins on
your BGA.

> I would also suggest that you definitely look into using separate 
> complete layers for power and ground under your BGA as opposed
> to trying to juggle split planes.

Jeez. How many layers does he have spare for power planes?? my BGA needed 3
of the buggers. Split planes are the only way to go. Just be really careful
not to bridge them with a through hole pin like I did... 



Julian
(who got his BGA board not reporting errors, and the BGA part of it is fine)



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