I won't say much about the reference mentioned other than to say that I have put that author's books into long term storage.
References that are on my desk include: "High Speed Digital Design" by Stephen Hall, Garrett Hall & James McCall "Noise Reduction Techniques in Electronic Systems" by Henry W. Ott plus the two Black Magic books by Johnson and Graham. On the subject of stackups, as far as I'm concerned every design is different and requires a planned individual stackup. Issues that influence my stackup planning (beyond having sufficient routing room) include: 1/ The proportion of critical traces (clocks, fast-edge traces and any other controlled impedance connections) to ordinary stuff. This will determine how many of your signal layers need to be controlled impedance. 2/ Total board thickness. Thin boards (e.g. PC-Cards) severely limit stackup design options. 3/ Analog signals. I do a lot of RF work where I need signals to always reference the same ground plane (since the inductance of vias and possibly capacitors to shift return currents from one reference plane to another is a big factor). 4/ EMC sensitivity. Some designs will always be in a metal enclosure, while others need to be EMC quiet from the get-go. (Of course, all designs should be in the latter category... :-) 5/ Whether fast propagating signals are required. Surface microstrip structures will propagate faster than buried microstrip or stripline traces. They'll also radiate more... 6/ Whether the nature of the design will allow outer layer ground as a (somewhat perforated) plane. 7/ Whether blind and/or buried vias are allowed. John Haddy -----Original Message----- From: Nathan Horsfield [mailto:[EMAIL PROTECTED] Sent: Tuesday, 3 June 2003 11:28 AM To: Protel EDA Forum Subject: Re: [PEDA] eight-layer stackup Michael The "text book" standard that is 1 signal 2 gnd 3 signal 4 gnd 5 pwr 6 signal 7 pwr 8 signal thou never actually using 8 layers this is all i can give you. Hope it helps. Nathan BTW the reference is PCB design techniques for emc compliance by mark montrose. 2nd Edition Michael Biggs wrote: > Anyone have a preferred method of stackup guidelines of web references >to layer stackups for 8 layers using four power planes and four signal >layers? I am torn between two methods being that I have two internal >power planes. Thanks for any help! Also I have a couple of BGA's on >this layout and when I run (using >Protel99SE) my DRC everything is great other than the "dogbones" I had >to route to the via on all the unused pins of the BGA. Any way to >create rules for this so I do not get violations during DRC? Thanks >again! > >MichaelB > > > -- Nathan Horsfield Inspiration Technology P/L Ph: +61 8 8211 9668 Fax: +61 8 8211 9658 www.instech.com.au * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
