Please see below.


----- Original Message -----
From: "Dennis Saputelli" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, June 04, 2003 4:30 PM
Subject: Re: [PEDA] eight-layer stackup

> you just use a via and short track in the component footprint design
> and then run update free primitives (yes i know they are not 'free')
> it works
> no drc probs

You are right, this does in fact work fine, and in fact is pretty close to
what I do normally anyway.

I normally use one separate component for the BGA pad pattern footprint, and
then make a second component that contains all of the dogbone traces and
vias and all of what I call the BGA "escape routing", which is all of the
inner routing on the different layers out to the edge of the BGA.

I keep all of the "escape routing" intact in its own component, which is
placed in the design directly on top of the BGA component footprint (with
free primitives updated)until I have everything in the area of the BGA
routed exactly the way I want it. This allows me to easily "edit" the
routing "internal" to the perimeter of the BGA in the Component Editor, and
use Update PCB and then as you point out, use the "update free primitives".
Once I get everything the way I like it, I then "release" all of the
"primitives" of the second component into the design, and then all of the
traces and vias become part of the design.

Using your methodology, I would just keep the dogbone traces and the vias as
part of my first component, rather then the second component which I
"release". For that matter, I could just keep everything from my normal
first BGA component and my second "routing" component, all in one component,
and never "release" any it, and just keep updating free primitives as I go

I guess it is all a matter of personal preferences.

I prefer to have a standard BGA pattern for a component, and have nothing
attached to it in the end product, and have all of my vias and traces and
routing as normal vias and traces in the end product of the board, where I
can go in and change things such as width or layer or whatever one at a time
just as a normal trace. This also allows me to do things like highlight a
net all the way to the BGA pad, and get the full length of the net in the
netlist report.

Most importantly, this method allows me to end up with a PCB that does not
have any non standard little hidden "tricks" in it that may not be seen by
the next person down the line to work on the board, or even forgotten by me
the next time I have to come back in a year or two and work on the design

In this sense, I would prefer to have the DRC "errors" showing right out
there in plain sight where they can be seen for what they are.

My whole point in this post and the earlier post where I discussed this DRC
"error" issue (see the thread on subject "quick question" on last Saturday
(5/31/03)) is simply that sometimes Protel DRC "errors" really are not
errors at all, and I would like a way to handle them. Certainly there are
ways to do tricks to make the little iridescent glow go away, but in some
cases I just learn to live with them.

I personally would rather have a Protel DRC "error" glowing here and there
(which I can simply reset so I do not have to look at them) in the design,
than have to play tricks here and there and do some non standard thing to
make the DRC happy.

I would rather have the DRC "error", which anyone could see was not a real
"error" anyway, then have to jump thru the "update free primitives" hoop on
the finished design that gets released to production and sent down the road
to the next designer who may work on the design a few years from now after I
am gone.

There is just something that bugs me about having to play tricks in a design
to make a screwed up piece of software happy, especially when the screwed up
piece of software in wrong half the time when it comes to DRC "errors"

> am i on the same page as this discussion or maybe i have missed
> something?

Yep. You are in fact on the exact same page.

> ds


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