If you used the construction you suggest you'd encounter a problem with
copper balance.

It would appear either during board manufacture or reflow, or both. 

The mass of copper on 2/3 is different to 4/5 so the board will be badly
bent or twisted.
(The coefficient of expansion of copper is different to prepreg and FR4).
The forces generated
on a layer during heating depend on the density of copper in any given area.

If you want a guide to PCB lay-up, I suggest you talk to your board house.
Ours publishes a
really useful guide, see www.graphic.plc.uk  Each houses capabilities differ
on their techniques and equipment, though there are general industry and
practical rules


-----Original Message-----
From: Matt Polak [mailto:[EMAIL PROTECTED]
Sent: 03 June 2003 10:12
To: Protel EDA Forum
Subject: Re: [PEDA] six or eight-layer (or more?) stackups

At 10:57 AM 6/3/2003 +0930, you wrote:
>The "text book" standard that  is
>1    signal
>2    gnd
>3    signal
>4    gnd
>5    pwr
>6    signal
>7    pwr
>8    signal
>thou never actually using 8 layers this is all i can give you. Hope it

         Out of curiosity, what is the typical textbook stackup for a 
six-layer board? Do you typically have two signal, two power, two ground 
planes, or can you have, say, three signals layers and two power and one 
ground plane? i.e.

1. signal
2. gnd
3. pwr
4. signal
5. pwr
6. signal

         I would imagine this should be fine if there are no plane splits, 
save for possibly some on 3, since all signal layers would be directly 
adjacent to at least one unbroken plane... Or is my thinking flawed on 
this? Four layer is easy, and eight makes sense... But how do you typically 
work up the more oddball ones like six or ten or (shudder) even twenty two? 
I am looking at a design now that I think will probably require at least 
three signal layers to route, but I think an eight-layer board would be 
something of an overkill and would like to stick to six.

         How do folks typically deal with distributing power to parts that 
require separate core and I/O, maybe different cores for different parts on 
the board? For instance, multiple FPGAs that require a 2.5v core and 3.3v 
IO, and a DSP which requires a 1.8v core and 3.3v IO? Obviously 3.3v should 
probably have it's own power plane across the board, but can you take an 
inner power layer (like #3 in the above example) and split it between 1.8v 
and 2.5v as needed to source the core voltages as and where needed?

         I've done four layer boards fine this far; my approach (under QFP 
FPGAs that required 2.5v core and 3.3v IO) was to pour a polygon-plane on 
the top signal layer under the chip, and to connect this to all of the 
necessary pins, decouple the living daylights out of it, and then run a 
very fat trace on the back of the board over to the 2.5v regulator. It 
seems to have worked just fine on the latest run of boards - very clean 
power being supplied to all of the core pins - but I'm always interested in 
other's approaches that may be better suited to these kinds of situations.

         Someone really needs to write a modern 'style guide' to multilayer 
PCB layout, y'know? Not just the math and theory covered in several of the 
better books out there, but one also covering component layout techniques, 
approaches to signal and bus routing, shapes and patterns of via layout for 
moving busses from one layer to the other nicely, how to route *special* 
signals (differential, controlled impedance, matched length, etc), how to 
efficiently break out BGAs, and so forth. Certainly would make life a 
little easier for us newbies! :D

-- Matt

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