Ray,

It is indeed possible to design a board where no external caps are
required BUT there are major caveats!

An interplane capacitor is indeed the best cap you'll ever get on
a board however the total capacitance available is limited. This
means that your design must be capable of working with this little
capacitance.

e.g. a chip drawing 30W at 3V rail (i.e. 10A average current), clocking
at 1GHz will require 0.01uC of charge per clock cycle. If the maximum
voltage ripple allowed is 10% then this chip requires a minimum of 33nF
decoupling cap. Note that this minimum is what's needed for an AVERAGE
current draw - most chips include state transitions where peak currents
are much higher, so more capacitance is needed in order to support
these peak transitions.

So, provided that you can satisfy both the average and peak current
requirements of your board with the available interplane cap, you don't
really need any discretes.

There aren't too many designs that I do where this is possible, though.
I have seen it done quite successfully - one tantalum at the power
connector was all there was.

In most boards, there is a need for discrete caps to support lower
frequency charge storage. Once these are on the board you WILL get
resonances developing between the interplane cap and the bulk caps. The
only ways to prevent these resonant nulls from getting in the way are:

1/ Find out where the nulls are and ensure that they aren't coincident
with frequencies of interest (remembering to cater for all process and
component tolerance spreads),

or

2/ Use a spread of capacitor values so that you swap one or two deep
resonant nulls for a swag of shallower ones spread across the spectrum.

Most designers go for option 2 since time pressure seems to get in the
way of designing and testing option 1 properly!

Remember that, if you use only one cap value (like 0.01uF) for all your
bypassing, you will get a very deep resonance null that may be where
you don't want it.

Cheers,

John Haddy


> -----Original Message-----
> From: Ray Mitchell [mailto:[EMAIL PROTECTED] 
> Sent: Wednesday, 4 June 2003 6:25 AM
> To: Protel EDA Forum
> Subject: Re: [PEDA] six or eight-layer (or more?) stackups - 
> Capacitance
> 
> 
> At 03:44 PM 6/3/2003 -0400, you wrote:
> > > I thought that the following stackup was prefered because 
> then every 
> > > signal is one layer from a ground plane.
> > >
> > >  1    signal
> > >  2    gnd
> > >  3    signal
> > >  4    pwr
> > >  5    pwr
> > >  6    signal
> > >  7    gnd
> > >  8    signal
> >
> >But then you don't have as good decoupling between your pwr and gnd 
> >planes, since they are farther apart.
> >
> >My stackup (as mentioned in an earlier post, and repeated 
> below) gives 
> >you copper balance, better decoupling, and your signals are 
> still only 
> >1 layer away from a pwr or gnd plane.  And since the pwr and 
> gnd planes 
> >are effectively the same thing to high frequencies, a signal 
> being next 
> >to a pwr plane is the same as that signal being next to a gnd plane.
> >
> >sig
> >gnd1
> >pwr1
> >sig
> >sig
> >gnd2
> >pwr2
> >sig
> >
> >While we are on this subject, I like to use 0.01 uF caps for 
> >decoupling, not the 0.1 uF caps you frequently see on 
> digital circuits.  
> >The reason is that 0.01 uF caps have a higher self-resonance 
> frequency 
> >than 0.1 uF caps, which makes them better able to decouple the 
> >high-speed transients that are so common in today's circuits.  Also, 
> >0.01 uF caps are less expensive and take up less space (0805 
> vs. 1206).
> 
> First, my experience regarding layout is minimal at best 
> since I seem to 
> exhaust all the wrong ways first.  I once took a class in 
> multilayer layout 
> and was told that the capacitance between the power/ground planes 
> themselves was sufficient for decoupling high frequencies and 
> that adding 
> capacitors could cause tuned circuits and troublesome 
> resonances.  I'm 
> simply asking, any views on that theory?
> 
> Ray 
> 
> 
> 



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