----- Original Message ----- 
From: "Phillip Stevens" <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Wednesday, June 04, 2003 7:22 AM
Subject: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance


> 
> 
> JH> 2/ Use a spread of capacitor values so that you swap one or two deep
> JH> resonant nulls for a swag of shallower ones spread across the spectrum.
> 
> I found this to be interesting.  I've just about finished reading "Digital
> Design for Interference Specifications" David l. Terrell, R.Kenneth
> Keenan, 1997,  Published by NewNes ISBN 0-7506-7282-X.
> 
> The authors seem to take the opposite position that (bulk capacitance aside)
> using the same value bypass caps lowers the overall ESR,  which (they
> say) results in a lower overall spectrum.  And that mixing (for example)
> .1uf and .01uf values is a bad idea.  In any case,  it was an interesting
> read.
> 
> I'd be curious if anyone else has views on this subject,  one way or the other..

The same advice comes from the book
Montrose: Printed Circuit Board Design Techniques

<quote>
When selecting parallel caps, it is important to remember that as the larger
value capacitor goes inductive, the smaller value cap is still capacitive. 
At a particular frequency, a LC circuit is developed between the 2 caps.
An infinite impedance could be generated with no decoupling benefit provided.
When this occurs, single-capacitor decoupling is all that one can use 
for this application.
</quote>
 
Regards, Norbert.





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