we have had great success panelizing in Protel as i mentioned previously

the only comment i see here as a real concern is the inability to DRC
the panel
i never had any trouble with the other issues raised here

what i have done when i was concerned about no DRC was to simply (using
a copy) 
delete all but one section, reload the nets and re-run the DRC and then
reiterate that

it should be pointed out that there is a distinction between 
what i would call 'our' panel and what might be called 
'their' panel (i.e. their being 'fabricators')

i certainly agree that the fabricator is best able to make judgments as
to material usage and other matters

when we panelize it is usually not to do the fabricator's job (since
will generally multi-up our multi-up) but rather to achieve some
specific objectives
for one example:
to create a set ('our panel') of *different* bds which are used together
as a set and which may be loaded and cleaned together as a set and
broken apart only at the final box build

in the case of a simple repetition of the same bd i agree that it is
best left to the fabs

Dennis Saputelli

Abd ul-Rahman Lomax wrote:
> At 11:20 AM 7/11/2003, you wrote:
> >we panelize in PCB everyday (without going the gerber route)
> >you have to be careful of course
> Indeed.
> As has been mentioned, P99SE is not the best tool for panelization.
> CAMtastic may be better, it is designed for that.
> Some layers in Protel are called "calculated" layers. This means that the
> layer is not literally present in the database, but is calculated depending
> on, for example, solder mask expansion rules. Inner planes are also
> calculated layers. So if you are copying a PCB for panelization, you should
> realize that the resulting panel is not DRCable. And there could indeed be
> problems.
> First of all, the copied primitives must have the correct net assignments,
> the copied components must have the same reference designators, etc. If you
> know how to do it, all this can be done.
> (1) Generally fabricators prefer to panelize, since they can make the
> panels fit their process requirements. They don't charge for panelization,
> as far as I have seen.
> (2) Sometimes designers panelize to produce more copies of a board being
> made by a prototype service that is cheap for, say, one or two or three
> copies of a board. These services typically panelize boards from different
> customers, that is one way they can make boards so cheaply. I know of one
> company, a major one, that explicitly prohibits such panelization by the
> customer.
> (3) When the desired board to be stuffed is, for example, a breakaway panel
> with multiple boards, broken apart after it is populated, it may be desired
> to panelize for one's assembly requirements. This is the major good reason
> for panelizing. But it is still better done in a CAM tool.
> (4) Because Protel is not really designed for panelization, it does not
> have tools for DRCing a panel; and because of the calculated layers, it is
> quite easy to have errors in the added board images. Note that if a
> fabricator does the panelization, it will be the fabricator's
> responsibility if there is an error in this process, not yours. (And I'm
> pretty sure you are not a fabricator or you would not be attempting to do
> panelization in Protel, you'd have a much more efficient CAM tool for doing
> it.)
> (5) Your Protel database will become enormous, which can slow you down in
> many ways.
> (6) Sending a single board's worth of gerbers plus a master panel layer
> (see below) to a fabricator with instructions to step and repeat everything
> but the master panel layer involves, for the fabricator, a few second's
> attention, it might literally be less than a minute. And the size of the
> transmitted data will be *much* smaller than for a complete panel. A file
> zip program is not going to notice that all those different numbers are
> actually the same data offset! Nowadays with high-speed lines, etc., we
> often forget the data transmission time issue. Until we try to put our
> plots on a floppy. Or we discover that the size of file attachments is
> limited by someone's mail system.
> One way that I've done panels in Protel, on the rare occasion that the job
> required it, was to make a PCB file have only one copy of the final
> (smaller) board. On a mech layer, the "master panel layer," I place track
> and text that will become part of the final panel that is *not* to be
> multiplied up. This would be, for example, legends or the outlines of cutouts.
> Then the gerbers are generated. In CAMtastic, the gerbers for everything
> except that master panel layer are imported and panelized, together with
> one copy of the master panel. If properly designed, it should all fit neatly.
> Now, if one *must* do it in Protel, I'd recommend reimporting gerbers to a
> new board file, to make a free-primitive, explicit image of every item to
> be multiplied. The rules for this board should be set so that calculated
> layers do not create any altered plot primitives; this image can be copied
> and pasted into every position. Because they are generated from gerbers,
> they will be identical when plotted to the primary (original, single) board.
> I'd set all solder mask expansions to a large negative number, for example.
> The reason is that the actual solder mask flashes should come from the
> original solder mask plot, which will have the correct aperture sizes
> according to the original design rule settings. The free pad primitives on,
> say, the bottom layer, would otherwise generate their own solder mask
> plots, which might differ from the rule-based settings in the original design.
> And if one finds an error in the primary board, resist the temptation to
> try to correct all the individual copies; not only is it faster and easier,
> usually, to do it with one board, but the process will be error-prone and
> not DRCd. Fix the one board and then do all the multiplication again. Doing
> it again should be just a matter of deleting all primitives in the panel
> file, reimporting the corrected gerber, hiding the master layer, selecting
> all, copying to the clipboard,, and then copying it as an array with the
> first instance in the same position as the imported gerber. It should be
> that simple and fast. In this case, the primitives will be duplicated in the
> So, again, as a lesson from the School of Hard Knocks, make sure the single
> board is correct before panelizing it! Consider panelization as part of the
> fabrication process rather than part of the design process (except that the
> panelization is itself designed....). When, for example, submitting the
> board for review by another engineer, don't make the full expanded panel!
> The master layer I mentioned is the panel design, and the design reviewer
> should be able to readily understand that; the actual multiplication of the
> board primitives (in Protel) or of the gerber code (in CAMtastic or another
> CAM program) is simply the final step before the films go to physical
> fabrication. Yes, the completed panel should be checked, but at this step
> one would be looking only for copy failures, not reviewing other aspects of
> the design.

Dennis Saputelli

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