Has anyone used the EDIF output format from P99SE, especially with
the PLD section of Protel 99SE?  I'm trying to get around the incredibly
hideous schematic package in Xilinx's ISE.  The most significant difference
is Protel seems to require the IPAD and OPAD components, and won't even
create a netlist through the PLD compiler without those components to
source the signals.  But, Xilinx DOESN'T want the IPAD and OPAD
components, it just wants ports on the top-level schematic page.

Has anyone figured out how to PLD-compile a schematic without IPAD
and OPAD parts for the device pins?

Alternatively, has anyone figured out how to get an EDIF file from a
multi-sheet schematic in Protel 99SE? Yes, I know, there is an EDIF
format selection in the Create Netlist command, but it appears to
produce a badly mangled netlist, and the Xilinx tools find many
complaints. Digging through the EDIF file produced this way, I
see reason for complaint, although I'm no EDIF expert. Primarily,
if the sheets are going to be represented as Cells, the ports on the
cell has to be defined first, before the cell is instantiated. But, using the
Create Netlist command, the definition of the sub-sheets are NOT there!
Only the master sheet is defined.
Obviously, Xilinx's tools can't work without the definitions of the
cell's ports.

Another problem with the EDIFs produced either way is that in the
definitions of the cells from the library, all ports are prefixed by the '&'
character, while in the netlist part, the ports are referred to by the PortRef
symbol WITHOUT the &. Obviously, that can't work. I just use a
text editor to remove all &'s from the file, as I can't see anywhere in
the Protel libraries where these &'s are coming from. The &'s cause the
symbol names not to match with the symbols in Xilinx's libraries, either.

Finally, either form of output seems to duplicate definitions of the library
components used in the design.  Xilinx can't handle that.  I don't know if
that is actually a violation of the EDIF format or not.

Does anyone have any comments on this?  If I can figure out how to get a
reasonably close rendition of the EDIF file, I should be able to write a
simple converter to make the corrections.

Thanks in advance,


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