When I initially sent this reply, I believe that I for some reason I hit some keys that somehow set a flag that required a varification of reception, and who knows what else, which appears from at least at my end here to have somehow disrupted normal distribition of the email to the list, resulting in my not getting either my cc back or the normal distribution copy (although I did get the verification (maby I sent a "blank")). I am therefore sending this reply a second time, and I apologize if this results in yet a second distribution of the same email to the list. - JaMi ==================================================
Mark, One way that I usually accomplish the task of placing all of the short traces and vias to the respective planes for all of my decoupling caps, or even for those resistors or capacitors that are in circuit but have one end tied either to a voltage plane or ground plane, is to define one trace, and one via, and then select them and then copy them with the location point of the copy being that of the center of the pad that is going to be grounded or tied hi. I can then use a keystroke combination of E P (edit place) using my little finger of my left hand on the E key and my thumb or index finger on the P key, and just do an E P followed by the placing of the copied trace and via with the mouse , using the space bar as necessary to do any rotating that may be necessary, and then once everything is positioned, I do a left click on the mouse to place everything. Then I simply repeat the process for the next location that needs a connection. Usually I can place a trace and via "pair" where ever I need them in a very short time, and I have not found it necessary to go to the extreme of having a special component, which would take even longer to define on the schematic (which would require a special "footprint") than I would spend even on a large number of such connections. Very occasionally (and I don't remember what the circumstances are) the copied trace and via will assume the net name of the pad which you are connecting to, but usually you will have do an "Update Free Primitives . . . " from the Drop Down List of the Menu Button in the lower Left Corner of the Netlist Manager (found in the Drop Down Menu under Design, once I have placed all of the trace and via "pairs". This copy technique works especially well if you follow the IPC-2221 guidelines that suggest doubling up the number of vias on decoupling caps, such that you need 2 vias, properly spaced, and a whole bunch of little trace segments to connect them to the center of the appropriate pad. This method usually gets the job done for me, although there are certainly other approaches to the problem, as have been described in other responses to your question. The nice thing about using a small narrow trace and a via that is placed a few mils away from the edge of the pad, as opposed to using an oblong pad as you mentioned, is that a small trace, although short, will provide enough "thermal isolation" from the connection to the power or ground plane, that it is not necessary to have any "thermal relief" on such a via where it connects to the plane. JaMi ----- Original Message ----- From: "Leopold, Mark" <[EMAIL PROTECTED]> To: <[EMAIL PROTECTED]> Sent: Wednesday, September 10, 2003 5:53 AM Subject: [PEDA] Footprints with traces Hi, I am running DXP and I want/need to create a footprint that has surface mount pads connected to vias by a short trace that won't cause a whole lot of DRC errors on my PCB. The footprint is for bypass caps placed on the component side of a multi-layer board. The vias take the cap terminals to the appropriate power or ground plane. My company's boards are not that complex and I generally hand route them, so this would save me from having to run traces and placing vias for all the bypass caps. I could also see this being useful for creating footprints that will accommodate both SMT and THT resistors and caps -- which I could have used more than once in the past when prototyping. The problem that I run into is that in the process of generating the PCB from the schematic, the pad is correctly associated with its intended net, but neither the trace nor the via are associated with any net. This leads to DRC clearance errors as I have effectively connected a No Net trace to a pad with a net. Is there any way to setup the footprint or the schematic to PCB process so that the pad-trace-via combination are all added to the appropriate net? Another possible solution that I toyed with was to have an elongated pad with the hole offset, but I can't find any way to have the hole placed anywhere but in the middle of the pad. Is there a way to place the hole offset from the middle of the pad? Thanks, Mark * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
