Mark,
        the best forum to ask DXP questions is on the Altium DXP technical forum. You 
can sign up for it through the Altium website.
        However, I believe this problem is the very same as one finds in P99SE. There 
is no way to have the tracks and additional pads or fills associated with a net 
automatically DRC error free when you enter the footprint into your PCB database. In 
the section for editing control of nets (sorry I don't use DXP so I can't say exactly 
where it is) there is a function called something similar to "Update free primitives 
from Component pads". After running this function your non-net associated tracks and 
fills will be updated to the same netname as the pads they are connected to.
        Hope that helps, someone else may answer shortly that uses DXP and can give 
you a more precise description of where the function lies in DXP.

        The only way to create offset holes as far as I know is to add additional 
copper tracks or fills to offset the pad area from the hole. For your task I would be 
thinking of using just fills the correct size for SMT bypass caps. If you are using 
thru hole caps, I think that I would just use separate components rather than building 
them in. With built in ancillary components you will have issues creating your 
schematic and BOMs because you will not be treating them as separate components.

Sincerely,
Brad Velander.

Lead PCB Designer
Norsat International Inc.
Microwave Products
Tel   (604) 292-9089 (direct line)
Fax  (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com


> -----Original Message-----
> From: Leopold, Mark [mailto:[EMAIL PROTECTED]
> Sent: Wednesday, September 10, 2003 5:54 AM
> To: [EMAIL PROTECTED]
> Subject: [PEDA] Footprints with traces
> 
> 
> Hi,
> 
> I am running DXP and I want/need to create a footprint that 
> has surface mount pads connected to vias by a short trace 
> that won't cause a whole lot of DRC errors on my PCB.
> 
> The footprint is for bypass caps placed on the component side 
> of a multi-layer board.  The vias take the cap terminals to 
> the appropriate power or ground plane.  My company's boards 
> are not that complex and I generally hand route them, so this 
> would save me from having to run traces and placing vias for 
> all the bypass caps.  I could also see this being useful for 
> creating footprints that will accommodate both SMT and THT 
> resistors and caps -- which I could have used more than once 
> in the past when prototyping.
> 
> The problem that I run into is that in the process of 
> generating the PCB from the schematic, the pad is correctly 
> associated with its intended net, but neither the trace nor 
> the via are associated with any net.  This leads to DRC 
> clearance errors as I have effectively connected a No Net 
> trace to a pad with a net.
> 
> Is there any way to setup the footprint or the schematic to 
> PCB process so that the pad-trace-via combination are all 
> added to the appropriate net?
> 
> Another possible solution that I toyed with was to have an 
> elongated pad with the hole offset, but I can't find any way 
> to have the hole placed anywhere but in the middle of the 
> pad.  Is there a way to place the hole offset from the middle 
> of the pad?
> 
> Thanks,
> 
> Mark


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