Did I mention before that I have 'habd ah dewwubuh cowd' ? It clearly affected my thinking....

Oh well, just found the solution to the problem:

I just need to uncheck the 'lock primitives' checkbox on the antenna footprint before running the 'update primitives'... And, of course, re-check the box afterwards.
The only snag is that it has to be done every time the PCB is updated from the schematic.


Sorry for the noise.

At 14/10/2003 13:04, I wrote:
<snip-snip>

The connection pads take on the correct nets, but generate DRC clearance errors on the tracks that are part of the footprint. Thanks to the virtual shorts and associated rules the loop itself is error-free, it's just the connection pads that generate the errors......

The 'update free primitives from component pads' command does not help since the violating primitives are not free (they are part of the footprint).
Releasing the footprint does not help much either, I then have an unplaced component....


Is there any way out of this?


Leo Potjewijd hardware designer IE Keyprocessor bv.

[EMAIL PROTECTED]
+31 20 4620700



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